Intel® 64 and IA-32 Architectures Optimization Reference Manual

OPTIMIZING FOR SIMD INTEGER APPLICATIONSExample 5-10. PINSRW Instruction Code; Input:; edx pointer to source value; Output:; mm0 register with new 16-bit value inserted;mov eax, [edx]pinsrw mm0, eax, 1If all of the operands in a register are being replaced by a series of PINSRW instructions,it can be useful to clear the content and break the dependence chain by eitherusing the PXOR instruction or loading the register. See Example 5-11 and Section3.5.1.6, “Clearing Registers and Dependency Breaking Idioms.”Example 5-11. Repeated PINSRW Instruction Code; Input:; edx pointer to structure containing source; values at offsets: of +0, +10, +13, and +24; immediate value: “1”; Output:; MMX register with new 16-bit value inserted;pxor mm0, mm0 ; Breaks dependency on previous value of mm0mov eax, [edx]pinsrw mm0, eax, 0mov eax, [edx+10]pinsrw mm0, eax, 1mov eax, [edx+13]pinsrw mm0, eax, 2mov eax, [edx+24]pinsrw mm0, eax, 35.4.8 Move Byte Mask to IntegerThe PMOVMSKB instruction returns a bit mask formed from the most significant bitsof each byte of its source operand. When used with 64-bit MMX registers, thisproduces an 8-bit mask, zeroing out the upper 24 bits in the destination register.When used with 128-bit XMM registers, it produces a 16-bit mask, zeroing out theupper 16 bits in the destination register.The 64-bit version of this instruction is shown in Figure 5-7 and Example 5-12.5-14