IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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APPLICATION PERFORMANCE TOOLSExample 10-8. Auto-Generated Code to Avoid Unaligned LoadsCompiler Switch QxWCompiler Switch QxT$B2$2movups xmm0, _src[eax+4]movaps xmm1, _src[eax]movaps xmm4, _src[eax+16]movsd xmm3, _src[eax+20]subps xmm1, xmm0subps xmm1, _src[eax+16]movss xmm2, _src[eax+28]movhps xmm2, _src[eax+32]movups _dst[eax+8], xmm1shufps xmm3, xmm2, 132subps xmm4, xmm3subps xmm4, _src[eax+32]movlps _dst[eax+24], xmm4movhps _dst[eax+32], xmm4add eax, 32cmp eax, 4064jb $B2$2$B2$2:movaps xmm2, _src[eax+16]movaps xmm0, _src[eax]movdqa xmm3, _src[eax+32]movdqa xmm1, xmm2palignr xmm3, xmm2, 4palignr xmm1, xmm0, 4subps xmm0, xmm1subps xmm0, _src[eax+16]movups _dst[eax+8], xmm0subps xmm2, xmm3subps xmm2, _src[eax+32]movlps _dst[eax+24], xmm2movhps _dst[eax+32], xmm2add eax, 32cmp eax, 4064jb $B2$2A.2 INTEL ® VTUNE PERFORMANCE ANALYZERThe Intel VTune Performance Analyzer is a powerful software-profiling tool forMicrosoft Windows and Linux. The VTune analyzer helps you understand the performancecharacteristics of your software at all levels: system, application, microarchitecture.The sections that follow describe the major features of the VTune analyzer and brieflyexplain how to use them. For more details on these features, run the VTune analyzerand see the online documentation.All features are available for Microsoft Windows. On Linux, sampling and call graphare available.A.2.1SamplingSampling allows you to profile all active software on your system, including operatingsystem, device driver, and application software. It works by occasionally interruptingthe processor and collecting the instruction address, process ID, and thread ID. Afterthe sampling activity completes, the VTune analyzer displays the data by process,thread, software module, function, or line of source. There are two methods forgenerating samples: Time-based sampling and Event-based sampling.A-10
APPLICATION PERFORMANCE TOOLSA.2.1.1Time-based SamplingTime-based sampling (TBS) uses an operating system’s (OS) timer to periodicallyinterrupt the processor to collect samples. The sampling interval is user definable.TBS is useful for identifying the software on your computer that is taking the mostCPU time. This feature is only available in the Windows version of the VTune AnalyzerA.2.1.2Event-based SamplingEvent-based sampling (EBS) can be used to provide detailed information on thebehavior of the microprocessor as it executes software. Some of the events that canbe used to trigger sampling include clockticks, cache misses, and branch mispredictions.The VTune analyzer indicates where micro architectural events, specific to theIntel Core microarchitecture, Pentium 4, Pentium M and Intel Xeon processors, occurthe most often. On processors based on Intel Core microarchitecture, it is possible tocollect up to 5 events (three events using fixed-function counters, two events usinggeneral-purpose counters) at a time from a list of over 400 events (see Appendix A,“Performance Monitoring Events” of Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 3B). On Pentium M processors, the VTune analyzer cancollect two different events at a time. The number of the events that the VTuneanalyzer can collect at once on the Pentium 4 and Intel Xeon processor depends onthe events selected.Event-based samples are collected periodically after a specific number of processorevents have occurred while the program is running. The program is interrupted,allowing the interrupt handling driver to collect the Instruction Pointer (IP), loadmodule, thread and process ID's. The instruction pointer is then used to derive thefunction and source line number from the debug information created at compile time.The Data can be displayed as horizontal bar charts or in more detail as spread sheetsthat can be exported for further manipulation and easy dissemination.A.2.1.3Workload CharacterizationUsing event-based sampling and processor-specific events can provide usefulinsights into the nature of the interaction between a workload and the microarchitecture.A few metrics useful for workload characterization are discussed in Appendix B.The event lists available on various Intel processors can be found in Appendix A,“Performance Monitoring Events” of Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 3B.A.2.2Call GraphCall graph helps you understand the relationships between the functions in yourapplication by providing timing and caller/callee (functions called) information. Callgraph works by instrumenting the functions in your application. Instrumentation isthe process of modifying a function so that performance data can be captured whenthe function is executed. Instrumentation does not change the functionality of theA-11
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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