IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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MULTICORE AND HYPER-THREADING TECHNOLOGYExample 8-11. Assembling 3-level IDs, Affinity Masks for Each Logical Processor (Contd.)typedef struct {AFFINITYMASK affinity_mask; // 8 byte in 64-bit mode,// 4 byte otherwise.unsigned char smt;; unsigned char core;unsigned char pkg;unsigned char initialAPIC_ID;} APIC_MAP_T;APIC_MAP_T apic_conf[64];ThreadAffinityMask = 1;ProcessorNum = 0;while (ThreadAffinityMask != 0 && ThreadAffinityMask
MULTICORE AND HYPER-THREADING TECHNOLOGY• Scheduling two functional-decomposition threads to use shared executionresources cooperatively• Scheduling pairs of memory-intensive threads and compute-intensive threads tomaximize processor scaling and avoid resource contentions in the same coreAn example using the 3-level hierarchy and relationships between the initial APIC_IDand the affinity mask to manage thread affinity binding is shown in Example 8-12.The example shows an implementation of building a lookup table so that thesequence of thread scheduling is mapped to an array of affinity masks such thatthreads are scheduled first to the primary logical processor of each processor core.This example is also optimized to the situations of scheduling two memory-intensivethreads to run on separate cores and scheduling two compute-intensive threads onseparate cores.User/Source Coding Rule 38. (M impact, L generality) Consider using threadaffinity to optimize sharing resources cooperatively in the same core andsubscribing dedicated resource in separate processor cores.Some multicore processor implementation may have a shared cache topology that isnot uniform across different cache levels. The deterministic cache parameter leaf ofCPUID will report such cache-sharing topology. The 3-level hierarchy and relationshipsbetween the initial APIC_ID and affinity mask can also be used to manage sucha topology.Example 8-13 illustrates the steps of discovering sibling logical processors in a physicalpackage sharing a target level cache. The algorithm assumes initial APIC IDs areassigned in a manner that respect bit field boundaries, with respect to the modularboundary of the subset of logical processor sharing that cache level. Software canquery the number of logical processors in hardware sharing a cache using the deterministiccache parameter leaf of CPUID. By comparing the relevant bits in the initialAPIC_ID, one can construct a mask to represent sibling logical processors that aresharing the same cache.Note the bit field boundary of the cache-sharing topology is not necessarily the sameas the core boundary. Some cache levels can be shared across core boundary.Example 8-12. Assembling a Look up Table to Manage Affinity Masksand Schedule Threads to Each Core FirstAFFINITYMASK LuT[64]; // A Lookup table to retrieve the affinity// mask we want to use from the thread// scheduling sequence index.int index =0; // Index to scheduling sequence.j = 0;8-37
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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Page 234 and 235: OPTIMIZING FOR SIMD FLOATING-POINT
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Page 294 and 295: OPTIMIZING CACHE USAGE• Take adva
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTo
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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