IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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CONTENTSExample 5-29. Clipping to an Arbitrary Unsigned Range [High, Low] . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27Example 5-28. Simplified Clipping to an Arbitrary Signed Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27Example 5-30. Complex Multiply by a Constant. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30Example 5-31. A Large Load after a Series of Small Stores (Penalty) . . . . . . . . . . . . . . . . . . . . . . . . . 5-32Example 5-32. Accessing Data Without Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32Example 5-33. A Series of Small Loads After a Large Store . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33Example 5-34. Eliminating Delay for a Series of Small Loads after a Large Store . . . . . . . . . . . . . . 5-33Example 5-35. An Example of Video Processing with Cache Line Splits . . . . . . . . . . . . . . . . . . . . . . . 5-34Example 5-36. Video Processing Using LDDQU to Avoid Cache Line Splits. . . . . . . . . . . . . . . . . . . . . 5-35Example 6-1. Pseudocode for Horizontal (xyz, AoS) Computation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-6Example 6-2. Pseudocode for Vertical (xxxx, yyyy, zzzz, SoA) Computation . . . . . . . . . . . . . . . . . . 6-7Example 6-3. Swizzling Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-8Example 6-4. Swizzling Data Using Intrinsics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-9Example 6-5. Deswizzling Single-Precision SIMD Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-10Example 6-6. Deswizzling Data Using the movlhps and shuffle Instructions. . . . . . . . . . . . . . . . . . 6-11Example 6-7. Deswizzling Data 128-bit Integer SIMD Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-12Example 6-8. Using MMX Technology Code for Copying or Shuffling. . . . . . . . . . . . . . . . . . . . . . . . . 6-13Example 6-9. Horizontal Add Using MOVHLPS/MOVLHPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-14Example 6-10. Horizontal Add Using Intrinsics with MOVHLPS/MOVLHPS . . . . . . . . . . . . . . . . . . . . . 6-15Example 6-11. Multiplication of Two Pair of Single-precision Complex Number . . . . . . . . . . . . . . . . 6-18Example 6-12. Division of Two Pair of Single-precision Complex Numbers . . . . . . . . . . . . . . . . . . . . 6-19Example 6-13. Double-Precision Complex Multiplication of Two Pairs . . . . . . . . . . . . . . . . . . . . . . . . . 6-20Example 6-14. Double-Precision Complex Multiplication Using Scalar SSE2 . . . . . . . . . . . . . . . . . . . . 6-20Example 6-15. Dot Product of Vector Length 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21Example 6-16. Unrolled Implementation of Four Dot Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-21Example 8-1. Serial Execution of Producer and Consumer Work Items. . . . . . . . . . . . . . . . . . . . . . . . 7-6Example 8-2. Basic Structure of Implementing Producer Consumer Threads . . . . . . . . . . . . . . . . . . 7-7Example 8-3. Thread Function for an Interlaced Producer Consumer Model. . . . . . . . . . . . . . . . . . . 7-9Example 8-4. Spin-wait Loop and PAUSE Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-17Example 8-5. Coding Pitfall using Spin Wait Loop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-20Example 8-6. Placement of Synchronization and Regular Variables. . . . . . . . . . . . . . . . . . . . . . . . . . 7-22Example 8-7. Declaring Synchronization Variables without Sharing a Cache Line . . . . . . . . . . . . . 7-22Example 8-8. Batched Implementation of the Producer Consumer Threads . . . . . . . . . . . . . . . . . . 7-29Example 8-9. Adding an Offset to the Stack Pointer of Three Threads . . . . . . . . . . . . . . . . . . . . . . 7-31Example 8-10. Adding a Pseudo-random Offset to the Stack Pointer in the Entry Function . . . . 7-33Example 8-11. Assembling 3-level IDs, Affinity Masks for Each Logical Processor . . . . . . . . . . . . . 7-35Example 8-12. Assembling a Look up Table to Manage Affinity Masks andSchedule Threads to Each Core First . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-37Example 8-13. Discovering the Affinity Masks for Sibling Logical ProcessorsSharing the Same Cache. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-38Example 9-1. Pseudo-code Using CLFLUSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-12Example 9-2. Populating an Array for Circular Pointer Chasing with Constant Stride . . . . . . . . . 8-14Example 9-3. Prefetch Scheduling Distance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-18Example 9-4. Using Prefetch Concatenation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-19Example 9-5. Concatenation and Unrolling the Last Iteration of Inner Loop . . . . . . . . . . . . . . . . . . 8-19Example 9-6. Data Access of a 3D Geometry Engine without Strip-mining . . . . . . . . . . . . . . . . . . . 8-25Example 9-7. Data Access of a 3D Geometry Engine with Strip-mining . . . . . . . . . . . . . . . . . . . . . . 8-25PAGExvi
CONTENTSExample 9-8. Using HW Prefetch to Improve Read-Once Memory Traffic. . . . . . . . . . . . . . . . . . . . .8-27Example 9-9. Basic Algorithm of a Simple Memory Copy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-32Example 9-10. A Memory Copy Routine Using Software Prefetch. . . . . . . . . . . . . . . . . . . . . . . . . . . . .8-33Example 9-11. Memory Copy Using Hardware Prefetch and Bus Segmentation . . . . . . . . . . . . . . . .8-35Example 10-2. Auto-Generated Code of Storing Absolutes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7Example 10-3. Changes Signs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7Example 10-1. Storing Absolute Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-7Example 10-5. Data Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8Example 10-4. Auto-Generated Code of Sign Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-8Example 10-7. Un-aligned Data Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9Example 10-6. Auto-Generated Code of Data Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-9Example 10-8. Auto-Generated Code to Avoid Unaligned Loads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-10Example D-1. Aligned esp-Based Stack Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3Example D-2. Aligned ebp-based Stack Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-5PAGExvii
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Page 4 and 5: CONTENTS2.3.1 Front End. . . . . .
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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