IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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GENERAL OPTIMIZATION GUIDELINES3.6.3 AlignmentAlignment of data concerns all kinds of variables:• Dynamically allocated variables• Members of a data structure• Global or local variables• Parameters passed on the stackMisaligned data access can incur significant performance penalties. This is particularlytrue for cache line splits. The size of a cache line is 64 bytes in the Pentium 4 andother recent Intel processors, including processors based on Intel Core microarchitecture.An access to data unaligned on 64-byte boundary leads to two memory accesses andrequires several µops to be executed (instead of one). Accesses that span 64-byteboundaries are likely to incur a large performance penalty, the cost of each stallgenerally are greater on machines with longer pipelines.Double-precision floating-point operands that are eight-byte aligned have betterperformance than operands that are not eight-byte aligned, since they are less likelyto incur penalties for cache and MOB splits. Floating-point operation on a memoryoperands require that the operand be loaded from memory. This incurs an additionalµop, which can have a minor negative impact on front end bandwidth. Additionally,memory operands may cause a data cache miss, causing a penalty.Assembly/Compiler Coding Rule 45. (H impact, H generality) Align data onnatural operand size address boundaries. If the data will be accessed with vectorinstruction loads and stores, align the data on 16-byte boundaries.For best performance, align data as follows:• Align 8-bit data at any address.• Align 16-bit data to be contained within an aligned 4-byte word.• Align 32-bit data so that its base address is a multiple of four.• Align 64-bit data so that its base address is a multiple of eight.• Align 80-bit data so that its base address is a multiple of sixteen.• Align 128-bit data so that its base address is a multiple of sixteen.A 64-byte or greater data structure or array should be aligned so that its baseaddress is a multiple of 64. Sorting data in decreasing size order is one heuristic forassisting with natural alignment. As long as 16-byte boundaries (and cache lines) arenever crossed, natural alignment is not strictly necessary (though it is an easy way toenforce this).Example 3-28 shows the type of code that can cause a cache line split. The codeloads the addresses of two DWORD arrays. 029E70FEH is not a 4-byte-alignedaddress, so a 4-byte access at this address will get 2 bytes from the cache line thisaddress is contained in, and 2 bytes from the cache line that starts at 029E700H. Onprocessors with 64-byte cache lines, a similar cache line split will occur every 8 iterations.3-48
GENERAL OPTIMIZATION GUIDELINESExample 3-28. Code That Causes Cache Line Splitmov esi, 029e70fehmov edi, 05be5260hBlockmove:mov eax, DWORD PTR [esi]mov ebx, DWORD PTR [esi+4]mov DWORD PTR [edi], eaxmov DWORD PTR [edi+4], ebxadd esi, 8add edi, 8sub edx, 1jnz BlockmoveFigure 3-2 illustrates the situation of accessing a data element that span acrosscache line boundaries.Address 029e70c1hAddress 029e70fehCache Line 029e70c0hIndex 0Cache Line 029e7100hIndex 0 cont'dIndex 1Index 15 Index 16Cache Line 029e7140hIndex 16 cont'd Index 17Index 31 Index 32Figure 3-2. Cache Line Split in Accessing Elements in a ArrayAlignment of code is less important for processors based on Intel NetBurst microarchitecture.Alignment of branch targets to maximize bandwidth of fetching cachedinstructions is an issue only when not executing out of the trace cache.Alignment of code can be an issue for the Pentium M, Intel Core Duo and Intel Core 2Duo processors. Alignment of branch targets will improve decoder throughput.3-49
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURES4.4.3
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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