IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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INSTRUCTION LATENCY AND THROUGHPUTTable C-3a. Streaming SIMD Extension 2 128-bit Integer InstructionsInstruction Latency 1 ThroughputDisplayFamily_DisplayModel06_0FH06_0EH06_0DH06_09H06_0FH06_0EH06_0DH06_09HCVTDQ2PS xmm, xmm 3 4 1 2CVTPS2DQ xmm, xmm 3 4 4 4 1 2 2 2CVTTPS2DQ xmm, xmm 3 4 4 4 1 2 2 2MASKMOVDQU xmm, xmm 8 2MOVD xmm, r32 1 1 1 1 0.5 0.5 0.5 0.5MOVD xmm, r64 1 N/A N/A N/A 0.5 N/A N/A N/AMOVD r32, xmm 1 1 1 1 1 1 1 1MOVD r64, xmm 1 N/A N/A N/A 0.33 N/A N/A N/AMOVDQA xmm, xmm 1 1 1 1 0.33 1 1 1MOVDQU xmm, xmm 1 1 1 1 0.5 1 1 1MOVDQ2Q mm, xmm 1 1 1 1 0.5 0.5 0.5MOVQ2DQ xmm, mm 1 1 1 1 1 1 1 1MOVQ xmm, xmm 1 1 1 0.33 1 1PACKSSWB/PACKSSDW/ 4 2 2 2 3 2 2 2PACKUSWB xmm, xmmPADDB/PADDW/PADDD xmm, 1 1 1 1 0.33 1 1 1xmmPADDSB/PADDSW/PADDUSB/PADDUSWxmm, xmm1 1 1 1 0.33 1 1 1PADDQ mm, mm 2 2 2 2 1 1 1 1PSUBQ mm, mm 2 2 2 2 1 1 1 1PADDQ/ PSUBQ 3 xmm, xmm 2 3 3 3 1 2 2 2PAND xmm, xmm 1 1 1 1 0.33 1 1 1PANDN xmm, xmm 1 1 1 0.33 1 1 1PAVGB/PAVGW xmm, xmm 1 1 1 1 0.5 1 1 1PCMPEQB/PCMPEQD/ 1 1 1 1 0.33 1 1 1PCMPEQW xmm, xmmPCMPGTB/PCMPGTD/PCMPG 1 1 1 1 0.33 1 1 1TW xmm, xmmPEXTRW r32, xmm, imm8 2 3 3 3 1 2 2 2PINSRW xmm, r32, imm8 3 2 2 2 1 2 2 2C-8
INSTRUCTION LATENCY AND THROUGHPUTTable C-3a. Streaming SIMD Extension 2 128-bit Integer Instructions (Contd.)Instruction Latency 1 ThroughputDisplayFamily_DisplayModel06_0FH06_0EH06_0DH06_09H06_0FH06_0EH06_0DHPMADDWD xmm, xmm 3 4 4 4 1 2 2 2PMAX xmm, xmm 1 1 1 1 0.5 1 1 1PMIN xmm, xmm 1 1 1 1 0.5 1 1 1PMOVMSKB 3 r32, xmm 1 1 4 1 1 1 3PMULHUW/PMULHW/ 3 4 4 4 1 2 2 2PMULLW xmm, xmmPMULUDQ mm, mm 3 4 4 4 1 1 1 1PMULUDQ xmm, xmm 3 8 8 8 1 2 2 2POR xmm, xmm 1 1 1 1 0.33 1 1 1PSADBW xmm, xmm 3 7 7 7 1 2 2 2PSHUFD xmm, xmm, imm8 2 2 2 2 2 2 2 2PSHUFHW xmm, xmm, imm8 1 1 1 1 1 1 1 1PSHUFLW xmm, xmm, imm8 1 1 1 1 1 1 1 1PSLLDQ xmm, imm8 2 4 4 4 2 3 3 3PSLLW/PSLLD/PSLLQ xmm, 2 2 2 2 1 2 2 2xmm/imm8PSRAW/PSRAD xmm, 2 2 2 2 1 2 2 2xmm/imm8PSRLDQ xmm, imm8 2 4 4 2 4 4PSRLW/PSRLD/PSRLQ xmm, 2 2 2 2 1 2 2 2xmm/imm8PSUBB/PSUBW/PSUBD xmm, 1 1 1 1 0.33 1 1 1xmmPSUBSB/PSUBSW/PSUBUSB/ 1 1 1 1 0.33 1 1 1PSUBUSW xmm, xmmPUNPCKHBW/PUNPCKHWD/P 3 2 2 2 3 2 2 2UNPCKHDQ xmm, xmmPUNPCKHQDQ xmm, xmm 1 1 1 1 1 1 1 1PUNPCKLBW/PUNPCKLWD/P 3 2 2 2 3 2 2 2UNPCKLDQ xmm, xmmPUNPCKLQDQ xmm, xmm 1 1 1 1 1 1 1 1PXOR xmm, xmm 1 1 1 1 0.33 1 1 1See Appendix C.3.2, “Table Footnotes”06_09HC-9
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESIn t
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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Page 388 and 389: USING PERFORMANCE MONITORING EVENTS
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Page 460 and 461: STACK ALIGNMENTThe solution to this
Page 462 and 463: STACK ALIGNMENTExample D-1. Aligned
Page 464 and 465: STACK ALIGNMENTExample D-2. Aligned
Page 466 and 467: STACK ALIGNMENTD-8
Page 468 and 469: SUMMARY OF RULES AND SUGGESTIONSret
Page 470 and 471: SUMMARY OF RULES AND SUGGESTIONSfou
Page 472 and 473: SUMMARY OF RULES AND SUGGESTIONSvar
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Page 476 and 477: SUMMARY OF RULES AND SUGGESTIONSCor
Page 478 and 479: SUMMARY OF RULES AND SUGGESTIONSE-1
Page 480 and 481: INDEXsummary of rules, E-1tuning hi
Page 482 and 483: INDEXevent ratios, B-50execution co
Page 484 and 485: INDEXprefetching, 8-5SFENCE instruc
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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