Intel® 64 and IA-32 Architectures Optimization Reference Manual

64-BIT MODE CODING GUIDELINESFor example, to sign-extend a byte into ESI, use:movsx rsi, BYTE PTR[rax]instead of:movsx esi, BYTE PTR[rax]If the next instruction uses the 32-bit form of esi register, the result will be the same.This optimization can also be used to break an unintended dependency. For example,if a program writes a 16-bit value to a register and then writes the register with an 8-bit value, if bits 15:8 of the destination are not needed, use the sign-extendedversion of writes when available.For example:mov r8w, r9w; Requires a merge to preserve; bits 63:15.mov r8b, r10b; Requires a merge to preserve bits 63:8Can be replaced with:movsx r8, r9w ; If bits 63:8 do not need to be; preserved.movsx r8, r10b ; If bits 63:8 do not need to; be preserved.In the above example, the moves to R8W and R8B both require a merge to preservethe rest of the bits in the register. There is an implicit real dependency on R8 betweenthe 'MOV R8W, R9W' and 'MOV R8B, R10B'. Using MOVSX breaks the real dependencyand leaves only the output dependency, which the processor can eliminatethrough renaming.Assembly/Compiler Coding Rule 68. (M impact, M generality) Sign extend to64-bits instead of sign extending to 32 bits, even when the destination will be usedas a 32-bit value.9.3 ALTERNATE CODING RULES FOR 64-BIT MODE9.3.1 Use 64-Bit Registers Instead of Two 32-Bit Registersfor 64-Bit ArithmeticLegacy 32-bit mode offers the ability to support extended precision integer arithmetic(such as 64-bit arithmetic). However, 64-bit mode offers native support for64-bit arithmetic. When 64-bit integers are desired, use the 64-bit forms of arithmeticinstructions.In 32-bit legacy mode, getting a 64-bit result from a 32-bit by 32-bit integer multiplyrequires three registers; the result is stobbred in 32-bit chunks in the EDX:EAX pair.When the instruction is available in 64-bit mode, using the 32-bit version of the9-3