Intel® 64 and IA-32 Architectures Optimization Reference Manual

USING PERFORMANCE MONITORING EVENTSin addition to the counting event. The additional sub-event information isincluded in column 3 as various tags. These are described in Appendix B.3,“Performance Metrics and Tagging Mechanisms.” For event names that appear inthis column, refer to the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volumes 3A & 3B.• Column 4 specifies the event mask bits for setting up count events. The addressof various model-specific registers (MSR), the event mask bits in Event SelectControl registers (ESCR), and the bit fields in Counter Configuration Controlregisters (CCCR) are described in the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volumes 3A & 3B.Metrics listed in Table B-1 through Table B-7 cover the following categories:• General — Operation not specific to any sub-system of the microarchitecture• Branching — Branching activities• Trace Cache and Front End — Front end activities and trace cache operationmodes• Memory — Memory operation related to the cache hierarch• Bus — Activities related to Front-Side Bus (FSB)• Characterization — Operations specific to the processor core• Machine ClearMetricNon-sleep clock ticksNon-halted clock ticksTable B-1. Performance Metrics - GeneralDescriptionThe number of clockticks while a processoris not in any sleepmodesThe number of clockticks that theprocessor is in nothalted nor in sleepEvent Name or MetricExpressionSee explanation oncounting clocks inSection B.1.2.Global_power_eventsEvent Mask ValueRequiredRUNNINGB-6