Intel® 64 and IA-32 Architectures Optimization Reference Manual

GENERAL OPTIMIZATION GUIDELINES3.6.11 Minimizing Bus LatencyEach bus transaction includes the overhead of making requests and arbitrations. Theaverage latency of bus read and bus write transactions will be longer if reads andwrites alternate. Segmenting reads and writes into phases can reduce the averagelatency of bus transactions. This is because the number of incidences of successivetransactions involving a read following a write, or a write following a read, arereduced.User/Source Coding Rule 11. (M impact, ML generality) If there is a blend ofreads and writes on the bus, changing the code to separate these bus transactionsinto read phases and write phases can help performance.Note, however, that the order of read and write operations on the bus is not the sameas it appears in the program.Bus latency for fetching a cache line of data can vary as a function of the accessstride of data references. In general, bus latency will increase in response toincreasing values of the stride of successive cache misses. Independently, buslatency will also increase as a function of increasing bus queue depths (the numberof outstanding bus requests of a given transaction type). The combination of thesetwo trends can be highly non-linear, in that bus latency of large-stride, bandwidthsensitivesituations are such that effective throughput of the bus system for dataparallelaccesses can be significantly less than the effective throughput of smallstride,bandwidth-sensitive situations.To minimize the per-access cost of memory traffic or amortize raw memory latencyeffectively, software should control its cache miss pattern to favor higher concentrationof smaller-stride cache misses.User/Source Coding Rule 12. (H impact, H generality) To achieve effectiveamortization of bus latency, software should favor data access patterns that resultin higher concentrations of cache miss patterns, with cache miss strides that aresignificantly smaller than half the hardware prefetch trigger threshold.3.6.12 Non-Temporal Store Bus TrafficPeak system bus bandwidth is shared by several types of bus activities, includingreads (from memory), reads for ownership (of a cache line), and writes. The datatransfer rate for bus write transactions is higher if 64 bytes are written out to the busat a time.Typically, bus writes to Writeback (WB) memory must share the system bus bandwidthwith read-for-ownership (RFO) traffic. Non-temporal stores do not require RFOtraffic; they do require care in managing the access patterns in order to ensure 64bytes are evicted at once (rather than evicting several 8-byte chunks).Although the data bandwidth of full 64-byte bus writes due to non-temporal stores istwice that of bus writes to WB memory, transferring 8-byte chunks wastes bus3-67