Intel® 64 and IA-32 Architectures Optimization Reference Manual

INSTRUCTION LATENCY AND THROUGHPUTTable C-2. Streaming SIMD Extension 3 SIMD Floating-point InstructionsInstruction Latency 1 Throughput Execution UnitDisplayFamily_DisplayModel 0F_03H 0F_03H 0F_03HADDSUBPD/ADDSUBPS 5 2 FP_ADDHADDPD/HADDPS 13 4 FP_ADD,FP_MISCHSUBPD/HSUBPS 13 4 FP_ADD,FP_MISCMOVDDUP xmm1, xmm2 4 2 FP_MOVEMOVSHDUP xmm1, xmm2 6 2 FP_MOVEMOVSLDUP xmm1, xmm2 6 2 FP_MOVESee Appendix C.3.2, “Table Footnotes”Table C-2a. Streaming SIMD Extension 3 SIMD Floating-point InstructionsInstruction Latency 1 ThroughputDisplayFamily_DisplayModel 06_0FH 06_0EH 06_0FH 06_0EHADDSUBPD/ADDSUBPS 3 4 1 2HADDPD xmm1, xmm2 5 4 2 2HADDPS xmm1, xmm2 9 6 4 4HSUBPD xmm1, xmm2 5 4 2 2HSUBPS xmm1, xmm2 9 6 4 4MOVDDUP xmm1, xmm2 1 1 1 1MOVSHDUP xmm1, xmm2 2 2 1 2MOVSLDUP xmm1, xmm2 2 2See Appendix C.3.2, “Table Footnotes”Table C-3. Streaming SIMD Extension 2 128-bit Integer InstructionsInstruction Latency 1 Throughput Execution Unit 2DisplayFamily_DisplayModel 0F_03H 0F_02H 0F_03H 0F_02H 0F_02HCVTDQ2PS 3 xmm, xmm 5 5 2 2 FP_ADDCVTPS2DQ 3 xmm, xmm 5 5 2 2 FP_ADDCVTTPS2DQ 3 xmm, xmm 5 5 2 2 FP_ADDMOVD xmm, r32 6 6 2 2 MMX_MISC,MMX_SHFTC-5