Intel® 64 and IA-32 Architectures Optimization Reference Manual

INSTRUCTION LATENCY AND THROUGHPUTTable C-4a. Streaming SIMD Extension 2 Double-precisionFloating-point Instructions (Contd.)Instruction Latency 1 ThroughputDisplayFamily_DisplayModel 06_0FH06_0EH06_0DH06_09H06_0FH06_0EH06_0DH06_09HMINSD xmm, xmm 3 3 3 3 1 1 1 1MOVAPD xmm, xmm 1 1 1 1 0.33 1 1 1MOVMSKPD r32, xmm 1 1 1 1 1 1 1 1MOVMSKPD r64, xmm 1 N/A N/A N/A 1 N/A N/A N/AMOVSD xmm, xmm 1 1 1 1 0.33 0.5 0.5 0.5MOVUPD xmm, xmm 1 1 1 1 0.5 1 1 1MULPD xmm, xmm 5 7 7 7 1 4 4 4MULSD xmm, xmm 5 5 5 5 1 2 2 2ORPD xmm, xmm 1 1 1 1 1 1 1 1SHUFPD xmm, xmm, imm8 1 2 2 2 1 2 2 2SQRTPD xmm, xmm 58 115 115 115 57 114 114 114SQRTSD xmm, xmm 58 58 58 58 57 57 57 57SUBPD xmm, xmm 3 4 4 4 1 2 2 2SUBSD xmm, xmm 3 3 3 3 1 1 1 1UCOMISD xmm, xmm 1 1 1 1 1 1UNPCKHPD xmm, xmm 1 1 1 1 1 1UNPCKLPD xmm, xmm 1 1 1 1 1 1XORPD 3 xmm, xmm 1 1 1 1 1 1See Appendix C.3.2, “Table Footnotes”Table C-5. Streaming SIMD Extension Single-precisionFloating-point InstructionsInstruction Latency 1 Throughput Execution Unit 2DisplayFamily_DisplayModel 0F_03H 0F_02H 0F_03H 0F_02H 0F_02HADDPS xmm, xmm 5 4 2 2 FP_ADDADDSS xmm, xmm 5 4 2 2 FP_ADDANDNPS 3 xmm, xmm 4 4 2 2 MMX_ALUANDPS 3 xmm, xmm 4 4 2 2 MMX_ALUCMPPS xmm, xmm 5 4 2 2 FP_ADDCMPSS xmm, xmm 5 4 2 2 FP_ADDC-13