Intel® 64 and IA-32 Architectures Optimization Reference Manual

INSTRUCTION LATENCY AND THROUGHPUTTable C-4a. Streaming SIMD Extension 2 Double-precisionFloating-point InstructionsInstruction Latency 1 ThroughputDisplayFamily_DisplayModel 06_0FH06_0EH06_0DH06_09H06_0FH06_0EH06_0DH06_09HADDPD xmm, xmm 3 4 4 4 1 2 2 2ADDSD xmm, xmm 3 3 3 3 1 1 1 1ANDNPD xmm, xmm 1 1 1 1 1 1 1 1ANDPD xmm, xmm 1 1 1 1 1 1 1 1CMPPD xmm, xmm, imm8 3 4 4 4 1 2 2 2CMPSD xmm, xmm, imm8 3 3 3 3 1 1 1 1COMISD xmm, xmm 1 1 1 1 1 1 1 1CVTDQ2PD xmm, xmm 5 1 4CVTDQ2PS xmm, xmm 4 1CVTPD2PI mm, xmm 5 1 3CVTPD2DQ xmm, xmm 4 5 1 3CVTPD2PS xmm, xmm 4 5 3 3 1 2 2 2CVTPI2PD xmm, mm 4 5 5 5 1 4CVT[T]PS2DQ xmm, xmm 3 1CVTPS2PD xmm, xmm 2 3 3 3 2 3 3 3CVTSD2SI r32, xmm 3 4 4 4 1 1 1 1CVT[T]SD2SI r64, xmm 3 N/A N/A N/A 1 N/A N/A N/ACVTSD2SS xmm, xmm 4 4 4 4 1 1 1 1CVTSI2SD xmm, r32 4 4 4 1 1 1 1CVTSI2SD xmm, r64 4 N/A N/A N/A 1 N/A N/A N/ACVTSS2SD xmm, xmm 2 2 2 2 2 2 2 2CVTTPD2PI mm, xmm 5 5 5 1 3CVTTPD2DQ xmm, xmm 4 1CVTTSD2SI r32, xmm 3 4 4 4 1 1 1 1DIVPD xmm, xmm 32 63 63 63 31 62 62 62DIVSD xmm, xmm 32 32 32 32 31 31 31 31MAXPD xmm, xmm 3 4 4 4 1 2 2 2MAXSD xmm, xmm 3 3 3 3 1 1 1 1MINPD xmm, xmm 3 4 4 4 1 2 2 2C-12