IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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USING PERFORMANCE MONITORING EVENTSReplay Metric Tags 11stL_cache_load_miss_retired2ndL_cache_load_miss_retiredTable B-8. Metrics That Utilize Replay Tagging MechanismBit field to set:IA32_PEBS_ENABLEBit field toset: MSR_PEBS_MATRIX_VERTAdditional MSRSee EventMaskParameter forReplay_eventBit 0, 24, 25 Bit 0 None NBOGUSBit 1, 24, 25 Bit 0 None NBOGUSDTLB_load_miss_retired Bit 2, 24, 25 Bit 0 None NBOGUSDTLB_store_miss_ Bit 2, 24, 25 Bit 1 None NBOGUSretiredDTLB_all_miss_retired Bit 2, 24, 25 Bit 0, Bit 1 None NBOGUSTagged_mispred_branchBit 15, 16, 24, 25 Bit 4 None NBOGUSMOB_load_replay_retiredBit 9, 24, 25 Bit 0 Select MOB_load_replay and set thePARTIAL_DATAandUNALGN_ADDRbitsSplit_load_retired Bit 10, 24, 25 Bit 0 SelectLoad_port_replayevent onSAAT_CR_ESCR1and set SPLIT_LDbitSplit_store_retiredBit 10, 24, 25 Bit 1 Select Store_port_replay event onSAAT_CR_ESCR0and set SPLIT_STbitNBOGUSNBOGUSNBOGUSNOTES:1. Certain kinds of μops cannot be tagged. These include I/O operations, UC and locked accesses,returns, and far transfers.B-36
USING PERFORMANCE MONITORING EVENTSB.3.2Tags for front_end_eventTable B-9 provides a list of the tags that are used by various metrics derived from thefront_end_event. The event names referenced in column 2 can be found from thePentium 4 processor performance monitoring events.Table B-9. Metrics That Utilize the Front-end Tagging MechanismFront-end MetricTags 1Memory_loadsMemory_storesAdditional MSRSet the TAGLOADS bit inUop_TypeSet the TAGSTORES bit inUop_TypeSee Event Mask Parameterfor Front_end_eventNBOGUSNBOGUSNOTES:1. May be some undercounting of front end events when there is an overflow or underflow of thefloating point stack.B.3.3Tags for execution_eventTable B-10 provides a list of the tags that are used by various metrics derived fromthe execution_event. These tags require programming an upstream ESCR to selectevent mask with its TagUop and TagValue bit fields. The event mask for the downstreamESCR is specified in column 4. The event names referenced in column 4 canbe found in the Pentium 4 processor performance monitoring events.Table B-10. Metrics That Utilize the Execution Tagging MechanismExecution Metric TagsPacked_SP_retiredScalar_SP_retiredUpstream ESCRSet the ALL bit inthe event maskand the TagUop bitin the ESCR ofpacked_SP_uop.Set the ALL bit inthe event maskand the TagUop bitin the ESCR ofscalar_SP_uop.Tag Value inUpstream ESCRSee Event MaskParameter forExecution_event1 NBOGUS01 NBOGUS0B-37
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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Page 354 and 355: APPLICATION PERFORMANCE TOOLSThe /f
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Page 370 and 371: USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTT
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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Intel Corp.999 CANADA PLACE,Suite 4
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