Intel® 64 and IA-32 Architectures Optimization Reference Manual

USING PERFORMANCE MONITORING EVENTSB.1.2.1Non-Halted Clock TicksNon-halted clock ticks can be obtained by programming the appropriate ESCR andCCCR following the recipe listed in the general metrics category in Table B-1. In addition,the T0_OS/T0_USR/T1_OS/T1_USR bits may be specified to qualify a specificlogical processor and kernel as opposed to user mode.B.1.2.2Non-Sleep Clock TicksPerformance monitoring counters can be configured to count clocks whenever theperformance monitoring hardware is not powered-down. To count “non-sleep clockticks” with a performance-monitoring counter:• Select one of the 18 counters.• Select any of the possible ESCRs whose events the selected counter can count,and set its event select to anything other than no_event. This may not seemnecessary, but the counter may be disabled in some cases if this is not done.• Turn threshold comparison on in the CCCR by setting the compare bit to 1.• Set the threshold to 15 and the complement to 1 in the CCCR. Since no event canever exceed this threshold, the threshold condition is met every cycle and thecounter counts every cycle. Note that this overrides any qualification (forexample: by CPL) specified in the ESCR.• Enable counting in the CCCR for that counter by setting the enable bit.The counts produced by the Non-halted and Non-sleep metrics are equivalent inmost cases if each physical package supports one logical processor and is not in anypower-saving states. The operating system may execute the HLT instruction andplace a physical processor in a power-saving state.On processors that support HT Technology, each physical package can support two ormore logical processors. Current implementations of HT Technology provide twological processors for each physical processor.While both logical processors can execute two threads simultaneously, one logicalprocessor may be halted to allow the other to execute without having to share executionresources. “Non-halted clock ticks” can be qualified to count the number of clockcycles for a logical processor that is not halted (the count may include the clockcycles required complete a transition into a halted state).A physical processor that supports HT Technology enters into a power-saving state ifall logical processors are halted.“Non-sleep clock ticks” use is based on the filtering mechanism in the CCCR. Thecount continues to increment as long as one logical processor is not halted or in apower-saving state. An application may indirectly cause a processor to enter into apower-saving state by using an OS service that transfers control to the OS's idle loop.The system idle loop may place the processor into a power-saving state after animplementation-dependent period if there is no work to do.B-4