Intel® 64 and IA-32 Architectures Optimization Reference Manual

USING PERFORMANCE MONITORING EVENTSB.1.2.3Time-Stamp CounterThe time-stamp counter increments whenever the sleep pin is not asserted or whenthe clock signal on the system bus is active. It is read using the RDTSC instruction.The difference in values between two reads (modulo 2**64) gives the number ofprocessor clocks between reads.The time-stamp counter and “Non-sleep clock ticks” counts should agree in practicallyall cases if the physical processor is not in power-saving states. However, it ispossible to have both logical processors in a physical package halted, which results inmost of the chip (including the performance monitoring hardware) being powereddown. In this situation, it is possible for the time-stamp counter to continue incrementingbecause the clock signal on the system bus is still active; but “non-sleepclock ticks” may no longer increment because the performance monitoring hardwareis in power-saving states.B.2 METRICS DESCRIPTIONS AND CATEGORIESPerformance metrics for Intel Pentium 4 and Intel Xeon processors are listed inTable B-1 through Table B-7. These performance metrics consist of recipes toprogram specific Pentium 4 and Intel Xeon processor performance monitoring eventsto obtain event counts that represent: number of instructions, cycles, or occurrences.The tables also include a ratios that are derived from counts of other performancemetrics.On processors that support HT Technology, performance counters and associatedmodel specific registers (MSRs) are extended to support HT Technology. A subset ofperformance monitoring events allow the event counts to be qualified by logicalprocessor. The interface for qualification of performance monitoring events by logicalprocessor is documented in Intel® 64 and IA-32 Architectures Software Developer’sManual, Volumes 3A & 3B. Other performance monitoring events produce countsthat are independent of which logical processor is associated with microarchitecturalevents. The qualification of the performance metrics support HT Technology is listedin Table B-11 and Table B-12.In Table B-1 through Table B-7, recipes for programming performance metrics usingperformance-monitoring events are arranged as follows:• Column 1 specifies the metric. The metric may be a single-event metric; forexample, the metric Instructions Retired is based on the counts of theperformance monitoring event instr_retired, using a specific set of event maskbits. Or the metric may be an expression built up from other metrics. Forexample, IPC is derived from two single-event metrics.• Column 2 provides a description of the metric in column 1. Please refer toAppendix B.1.1, “Pentium® 4 Processor-Specific Terminology,” for terms that arespecific to the Pentium 4 processor’s capabilities.• Column 3 specifies the performance monitoring events or algebraic expressionsthat form metrics. There are several metrics that require yet another sub-eventB-5