Intel® 64 and IA-32 Architectures Optimization Reference Manual

INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURESOn processors without a third level cache, the second-level cache miss initiates atransaction across the system bus interface to the memory sub-system. On processorswith a third level cache, the third-level cache miss initiates a transaction acrossthe system bus. A bus write transaction writes 64 bytes to cacheable memory, orseparate 8-byte chunks if the destination is not cacheable. A bus read transactionfrom cacheable memory fetches two cache lines of data.The system bus interface supports using a scalable bus clock and achieves an effectivespeed that quadruples the speed of the scalable bus clock. It takes on the orderof 12 processor cycles to get to the bus and back within the processor, and 6-12 buscycles to access memory if there is no bus congestion. Each bus cycle equals severalprocessor cycles. The ratio of processor clock speed to the scalable bus clock speedis referred to as bus ratio. For example, one bus cycle for a 100 MHz bus is equal to15 processor cycles on a 1.50 GHz processor. Since the speed of the bus is implementation-dependent,consult the specifications of a given system for further details.2.2.4.4 Data PrefetchThe Pentium 4 processor and other processors based on the NetBurst microarchitecturehave two type of mechanisms for prefetching data: software prefetch instructionsand hardware-based prefetch mechanisms.Software controlled prefetch is enabled using the four prefetch instructions(PREFETCHh) introduced with SSE. The software prefetch is not intended forprefetching code. Using it can incur significant penalties on a multiprocessor systemif code is shared.Software prefetch can provide benefits in selected situations. These situationsinclude when:• the pattern of memory access operations in software allows the programmer tohide memory latency• a reasonable choice can be made about how many cache lines to fetch ahead ofthe line being execute• a choice can be made about the type of prefetch to useSSE prefetch instructions have different behaviors, depending on cache levelsupdated and the processor implementation. For instance, a processor may implementthe non-temporal prefetch by returning data to the cache level closest to theprocessor core. This approach has the following effect:• minimizes disturbance of temporal data in other cache levels• avoids the need to access off-chip caches, which can increase the realizedbandwidth compared to a normal load-miss, which returns data to all cache levelsSituations that are less likely to benefit from software prefetch are:• For cases that are already bandwidth bound, prefetching tends to increasebandwidth demands.2-29