IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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USING PERFORMANCE MONITORING EVENTSin addition to the counting event. The additional sub-event information isincluded in column 3 as various tags. These are described in Appendix B.3,“Performance Metrics and Tagging Mechanisms.” For event names that appear inthis column, refer to the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volumes 3A & 3B.• Column 4 specifies the event mask bits for setting up count events. The addressof various model-specific registers (MSR), the event mask bits in Event SelectControl registers (ESCR), and the bit fields in Counter Configuration Controlregisters (CCCR) are described in the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volumes 3A & 3B.Metrics listed in Table B-1 through Table B-7 cover the following categories:• General — Operation not specific to any sub-system of the microarchitecture• Branching — Branching activities• Trace Cache and Front End — Front end activities and trace cache operationmodes• Memory — Memory operation related to the cache hierarch• Bus — Activities related to Front-Side Bus (FSB)• Characterization — Operations specific to the processor core• Machine ClearMetricNon-sleep clock ticksNon-halted clock ticksTable B-1. Performance Metrics - GeneralDescriptionThe number of clockticks while a processoris not in any sleepmodesThe number of clockticks that theprocessor is in nothalted nor in sleepEvent Name or MetricExpressionSee explanation oncounting clocks inSection B.1.2.Global_power_eventsEvent Mask ValueRequiredRUNNINGB-6
USING PERFORMANCE MONITORING EVENTSMetricInstructions RetiredNon-Sleep CPINon-Halted CPIμops RetiredUPCSpeculative μopsRetiredTable B-1. Performance Metrics - General (Contd.)DescriptionNon-bogusinstructions executedto completionMay count more thanonce for someinstructions withcomplex μop flow or ifinstructions wereinterrupted beforeretirement. The countmay vary dependingon themicroarchitecturalstates when countingbegins.Cycles per instructionfor a physicalprocessor packageCycles per instructionfor a logical processorNon-bogus μopsexecuted tocompletionμop per cycle for alogical processorNumber of μopsretiredThis includesinstructions executedto completion andspeculatively executedin the path of branchmispredictions.Event Name or MetricExpressionInstr_retired NBOGUSNTAG |NBOGUSTAG(Non-Sleep Clock Ticks)/ (Instructions Retired)(Non-Halted ClockTicks) / (InstructionsRetired)μops_retiredμops Retired/ Non-Halted Clock Ticksμops_retiredEvent Mask ValueRequiredNBOGUSNBOGUS | BOGUSB-7
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESIn t
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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Page 354 and 355: APPLICATION PERFORMANCE TOOLSThe /f
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTo
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INSTRUCTION LATENCY AND THROUGHPUTT
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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