Intel® 64 and IA-32 Architectures Optimization Reference Manual

INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURESFigure 2-6. The Intel Pentium M Processor Microarchitecture2.3.1 Front EndThe Intel Pentium M processor uses a pipeline depth that enables high performanceand low power consumption. It’s shorter than that of the Intel NetBurst microarchitecture.The Intel Pentium M processor front end consists of two parts:• fetch/decode unit• instruction cacheThe fetch and decode unit includes a hardware instruction prefetcher and threedecoders that enable parallelism. It also provides a 32-KByte instruction cache thatstores un-decoded binary instructions.The instruction prefetcher fetches instructions in a linear fashion from memory if thetarget instructions are not already in the instruction cache. The prefetcher isdesigned to fetch efficiently from an aligned 16-byte block. If the modulo 16remainder of a branch target address is 14, only two useful instruction bytes arefetched in the first cycle. The rest of the instruction bytes are fetched in subsequentcycles.The three decoders decode instructions and break them down into µops. In eachclock cycle, the first decoder is capable of decoding an instruction with four or fewer2-33