Intel® 64 and IA-32 Architectures Optimization Reference Manual

INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURESTable 2-6. Trigger Threshold and CPUID Signatures for Processor FamiliesTrigger Threshold Distance(Bytes)ExtendedModel IDExtendedFamily ID Family ID Model ID512 0 0 15 3, 4, 6256 0 0 15 0, 1, 2256 0 0 6 9, 13, 14Data is fetched 64 bytes at a time; the instruction and data translation lookasidebuffers support 128 entries. See Table 2-7 for processor cache parameters.Table 2-7. Cache Parameters of Pentium M, Intel Core Solo,and Intel Core Duo ProcessorsLevel CapacityAssociativity(ways)Line Size(bytes)AccessLatency(clocks)Write UpdatePolicyFirst 32 KByte 8 64 3 WritebackInstruction 32 KByte 8 N/A N/A N/ASecond 1 MByte 8 64 9 Writeback(mode 9)Second 2 MByte 8 64 10 Writeback(model 13)Second(model 14)2 MByte 8 64 14 Writeback2.3.3 Out-of-Order CoreThe processor core dynamically executes µops independent of program order. Thecore is designed to facilitate parallel execution by employing many buffers, issueports, and parallel execution units.The out-of-order core buffers µops in a Reservation Station (RS) until their operandsare ready and resources are available. Each cycle, the core may dispatch up to fiveµops through the issue ports.2.3.4 In-Order RetirementThe retirement unit in the Pentium M processor buffers completed µops is the reorderbuffer (ROB). The ROB updates the architectural state in order. Up to three µops maybe retired per cycle.2-35