Intel® 64 and IA-32 Architectures Optimization Reference Manual

OPTIMIZING FOR SIMD INTEGER APPLICATIONSExample 5-16. Reverse Code, Using 3 Instructions/* Goal: Reverse the order of the words *//* Instruction Result */| 7| 6| 5| 4| 3| 2| 1| 0|PSHUFLW (0,1,2,3)| 7| 6| 5| 4| 0| 1| 2| 3|PSHUFHW (0,1,2,3)| 4| 5| 6| 7| 0| 1| 2| 3|PSHUFD (1,0,3,2) | 0| 1| 2| 3| 4| 5| 6| 7|5.4.11 Shuffle BytesSSSE3 provides PSHUFB; this instruction carries out byte manipulation within a 16byte range. PSHUFB can replace up to 12 other instructions: including SHIFT, OR,AND and MOV.Use PSHUFB if the alternative uses 5 or more instructions.5.4.12 Unpacking/interleaving 64-bit Data in 128-bit RegistersThe PUNPCKLQDQ/PUNPCHQDQ instructions interleave the low/high-order 64-bits ofthe source operand and the low/high-order 64-bits of the destination operand. Itthen writes the results to the destination register.The high/low-order 64-bits of the source operands are ignored.5.4.13 Data MovementThere are two additional instructions to enable data movement from 64-bit SIMDinteger registers to 128-bit SIMD registers.The MOVQ2DQ instruction moves the 64-bit integer data from an MMX register(source) to a 128-bit destination register. The high-order 64 bits of the destinationregister are zeroed-out.The MOVDQ2Q instruction moves the low-order 64-bits of integer data from a128-bit source register to an MMX register (destination).5.4.14 Conversion InstructionsSSE provides Instructions to support 4-wide conversion of single-precision datato/from double-word integer data. Conversions between double-precision data anddouble-word integer data have been added in SSE2.5-18