Intel® 64 and IA-32 Architectures Optimization Reference Manual

USING PERFORMANCE MONITORING EVENTSTable B-12. Metrics Supporting Qualification byLogical Processor and Parallel CountingGeneral Metricsμops RetiredInstructions RetiredInstructions CompletedSpeculative Instructions CompletedNon-Halted Clock TicksSpeculative Uops RetiredBranching MetricsBranches RetiredTagged Mispredicted Branches RetiredMispredicted Branches RetiredAll returnsAll indirect branchesAll callsAll conditionalsMispredicted returnsMispredicted indirect branchesMispredicted callsMispredicted conditionalsTC and Front End MetricsTrace Cache MissesITLB MissesTC to ROM TransfersTC FlushesSpeculative TC-Built μopsSpeculative TC-Delivered μopsSpeculative Microcode μopsMemory Metrics Split Load Replays 1Split Store Replays 1MOB Load Replays 164k Aliasing Conflicts1st-Level Cache Load Misses Retired2nd-Level Cache Load Misses RetiredDTLB Load Misses RetiredSplit Loads Retired 1Split Stores Retired 1MOB Load Replays RetiredLoads RetiredStores RetiredDTLB Store Misses RetiredDTLB Load and Store Misses Retired2nd-Level Cache Read Misses2nd-Level Cache Read References3rd-Level Cache Read Misses3rd-Level Cache Read ReferencesB-40