IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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MULTICORE AND HYPER-THREADING TECHNOLOGYRankings are subjective and approximate. They can vary depending on coding style,application and threading domain. The purpose of including high, medium and lowimpact ranking with each recommendation is to provide a relative indicator as to thedegree of performance gain that can be expected when a recommendation is implemented.It is not possible to predict the likelihood of a code instance across many applications,so an impact ranking cannot be directly correlated to application-level performancegain. The ranking on generality is also subjective and approximate.Coding recommendations that do not impact all three scaling factors are typicallycategorized as medium or lower.8.4 THREAD SYNCHRONIZATIONApplications with multiple threads use synchronization techniques in order to ensurecorrect operation. However, thread synchronization that are improperly implementedcan significantly reduce performance.The best practice to reduce the overhead of thread synchronization is to start byreducing the application’s requirements for synchronization. Intel Thread Profiler canbe used to profile the execution timeline of each thread and detect situations whereperformance is impacted by frequent occurrences of synchronization overhead.Several coding techniques and operating system (OS) calls are frequently used forthread synchronization. These include spin-wait loops, spin-locks, critical sections, toname a few. Choosing the optimal OS call for the circumstance and implementingsynchronization code with parallelism in mind are critical in minimizing the cost ofhandling thread synchronization.SSE3 provides two instructions (MONITOR/MWAIT) to help multithreaded softwareimprove synchronization between multiple agents. In the first implementation ofMONITOR and MWAIT, these instructions are available to operating system so thatoperating system can optimize thread synchronization in different areas. Forexample, an operating system can use MONITOR and MWAIT in its system idle loop(known as C0 loop) to reduce power consumption. An operating system can also useMONITOR and MWAIT to implement its C1 loop to improve the responsiveness of theC1 loop. See Chapter 7 in the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volume 3A.8.4.1 Choice of Synchronization PrimitivesThread synchronization often involves modifying some shared data while protectingthe operation using synchronization primitives. There are many primitives to choosefrom. Guidelines that are useful when selecting synchronization primitives are:• Favor compiler intrinsics or an OS provided interlocked API for atomic updates ofsimple data operation, such as increment and compare/exchange. This will be8-14
MULTICORE AND HYPER-THREADING TECHNOLOGYmore efficient than other more complicated synchronization primitives withhigher overhead.For more information on using different synchronization primitives, see thewhite paper Developing Multi-threaded Applications: A Platform ConsistentApproach. See http://www3.intel.com/cd/ids/developer/asmona/eng/53797.htm.• When choosing between different primitives to implement a synchronizationconstruct, using Intel Thread Checker and Thread Profiler can be very useful indealing with multithreading functional correctness issue and performance impactunder multi-threaded execution. Additional information on the capabilities ofIntel Thread Checker and Thread Profiler are described in Appendix A.Table 8-1 is useful for comparing the properties of three categories of synchronizationobjects available to multi-threaded applications.CharacteristicsCycles to acquireand release (ifthere is acontention)PowerconsumptionScheduling andcontextswitchingTable 8-1. Properties of Synchronization ObjectsOperating SystemSynchronization ObjectsThousands or Tens ofthousands cyclesSaves power by halting thecore or logical processor ifidleReturns to the OS schedulerif contention exists (can betuned with earlier spin loopcount)Light Weight UserSynchronizationHundreds of cyclesSome power saving ifusing PAUSEDoes not return to OSscheduler voluntarilySynchronizationObject based onMONITOR/MWAITHundreds of cyclesSaves more powerthan PAUSEDoes not return to OSscheduler voluntarilyRing level Ring 0 Ring 3 Ring 0Miscellaneous Some objects provide intraprocessMust lock accesses to Same as light weight.synchronization and synchronizationCan be used only onsome are for inter-process variable if severalsystems supportingcommunicationthreads may write to itMONITOR/MWAITsimultaneously.Otherwise can writewithout locks.8-15
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUT
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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