Intel® 64 and IA-32 Architectures Optimization Reference Manual

MULTICORE AND HYPER-THREADING TECHNOLOGY(such as a critical section) should be allocated to reside alone in a 128-byte regionand aligned to a 128-byte boundary.Example 8-6 shows a way to minimize the bus traffic required to maintain cachecoherency in MP systems. This technique is also applicable to MP systems usingprocessors with or without HT Technology.Example 8-6. Placement of Synchronization and Regular Variablesint regVar;int padding[32];int SynVar[32*NUM_SYNC_VARS];int AnotherVar;On Pentium M, Intel Core Solo, Intel Core Duo processors, and processors based onIntel Core microarchitecture; a synchronization variable should be placed alone andin separate cache line to avoid false-sharing. Software must not allow a synchronizationvariable to span across page boundary.User/Source Coding Rule 24. (M impact, ML generality) Place eachsynchronization variable alone, separated by 128 bytes or in a separate cacheline.User/Source Coding Rule 25. (H impact, L generality) Do not place any spinlock variable to span a cache line boundary.At the code level, false sharing is a special concern in the following cases:• Global data variables and static data variables that are placed in the same cacheline and are written by different threads.• Objects allocated dynamically by different threads may share cache lines. Makesure that the variables used locally by one thread are allocated in a manner toprevent sharing the cache line with other threads.Another technique to enforce alignment of synchronization variables and to avoid acacheline being shared is to use compiler directives when declaring data structures.See Example 8-7.Example 8-7. Declaring Synchronization Variables without Sharing a Cache Line__declspec(align(64)) unsigned __int64 sum;struct sync_struct {…};__declspec(align(64)) struct sync_struct sync_var;8-22