Intel® 64 and IA-32 Architectures Optimization Reference Manual

USING PERFORMANCE MONITORING EVENTSMetricBus Accesses fromthe ProcessorNon-prefetch BusAccesses from theProcessorPrefetch RatioFSB Data ReadyTable B-5. Performance Metrics - BusDescriptionNumber of all bustransactions allocatedin the IO Queue fromthis processorBeware of granularityissues with this event.Also Beware ofdifferent recipes inmask bits for Pentium4 and Intel Xeonprocessors betweenCPUID model fieldvalue of 2 and modelvalue less than 2.Number of all bustransactions allocatedin the IO Queue fromthis processor,excluding prefetchedsectors.Beware of granularityissues with this event.Also Beware ofdifferent recipes inmask bits for Pentium4 and Intel Xeonprocessors betweenCPUID model fieldvalue of 2 and modelvalue less than 2.Fraction of all bustransactions (includingretires) that were forHW or SW prefetching.Number of front-sidebus clocks that the busis transmitting datadriven by thisprocessorThis includes fullreads|writes andpartial reads|writesand implicitwritebacks.Event Name or MetricExpressionIOQ_allocationIOQ_allocation(Bus Accesses –Nonprefetch BusAccesses)/ (BusAccesses)Event Mask ValueRequired1a. ReqA0, ALL_READ,ALL_WRITE, OWN,PREFETCH (CPUIDmodel < 2);1b. ReqA0, ALL_READ,ALL_WRITE,MEM_WB, MEM_WT,MEM_WP, MEM_WC,MEM_UC, OWN,PREFETCH (CPUIDmodel >= 2).2: Enable edgefiltering 1 in theCCCR.1a. ReqA0, ALL_READ,ALL_WRITE, OWN(CPUID model < 2);1b. ReqA0, ALL_READ,ALL_WRITE,MEM_WB, MEM_WT,MEM_WP, MEM_WC,MEM_UC, OWN(CPUID model < 2).2: Enable edgefiltering 1 in theCCCR.FSB_data_activity 1: DRDY_OWN,DRDY_DRV2: Enable edgefiltering 1 in theCCCR.B-17