Intel® 64 and IA-32 Architectures Optimization Reference Manual

OPTIMIZING CACHE USAGEHardware prefetch mechanisms of processors based on Intel Core microarchitectureare discussed in Section 3.7.3 and Section 3.7.4. Despite differences in hardwareimplementation technique, the overall benefit of hardware prefetching to softwareare similar between Intel Core microarchitecture and prior microarchitectures.9.3 PREFETCH AND CACHEABILITY INSTRUCTIONSThe PREFETCH instruction, inserted by the programmers or compilers, accesses aminimum of two cache lines of data on the Pentium 4 processor prior to the dataactually being needed (one cache line of data on the Pentium M processor). Thishides the latency for data access in the time required to process data already residentin the cache.Many algorithms can provide information in advance about the data that is to berequired. In cases where memory accesses are in long, regular data patterns; theautomatic hardware prefetcher should be favored over software prefetches.The cacheability control instructions allow you to control data caching strategy inorder to increase cache efficiency and minimize cache pollution.Data reference patterns can be classified as follows:• Temporal — Data will be used again soon• Spatial — Data will be used in adjacent locations (for example, on the samecache line).• Non-temporal — Data which is referenced once and not reused in theimmediate future (for example, for some multimedia data types, as the vertexbuffer in a 3D graphics application).These data characteristics are used in the discussions that follow.9.4 PREFETCHThis section discusses the mechanics of the software PREFETCH instructions. Ingeneral, software prefetch instructions should be used to supplement the practice oftuning an access pattern to suit the automatic hardware prefetch mechanism.9.4.1 Software Data PrefetchThe PREFETCH instruction can hide the latency of data access in performance-criticalsections of application code by allowing data to be fetched in advance of actualusage. PREFETCH instructions do not change the user-visible semantics of aprogram, although they may impact program performance. PREFETCH merelyprovides a hint to the hardware and generally does not generate exceptions or faults.9-4