Intel® 64 and IA-32 Architectures Optimization Reference Manual

INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURESPort 0. In the first half of the cycle, port 0 can dispatch either one floating-pointmove µop (a floating-point stack move, floating-point exchange or floating-pointstore data) or one arithmetic logical unit (ALU) µop (arithmetic, logic, branch or storedata). In the second half of the cycle, it can dispatch one similar ALU µop.Port 1. In the first half of the cycle, port 1 can dispatch either one floating-pointexecution (all floating-point operations except moves, all SIMD operations) µop orone normal-speed integer (multiply, shift and rotate) µop or one ALU (arithmetic)µop. In the second half of the cycle, it can dispatch one similar ALU µop.Port 2. This port supports the dispatch of one load operation per cycle.Port 3. This port supports the dispatch of one store address operation per cycle.The total issue bandwidth can range from zero to six µops per cycle. Each pipelinecontains several execution units. The µops are dispatched to the pipeline that correspondsto the correct type of operation. For example, an integer arithmetic logic unitand the floating-point execution units (adder, multiplier, and divider) can share apipeline.Port 0Port 1Port 2 Port 3ALU 0DoubleSpeedFPMoveALU 1DoubleSpeedIntegerOperationNormalSpeedFPExecuteMemoryLoadMemoryStoreADD/SUBLogicStore DataBranchesFP MoveFP Store DataFXCHADD/SUBShift/RotateFP_ADDFP_MULFP_DIVFP_MISCMMX_SHFTMMX_ALUMMX_MISCAll LoadsPrefetchStoreAddressNote:FP_ADD refers to x87 FP, and SIMD FP add and subtract operationsFP_MUL refers to x87 FP, and SIMD FP multiply operationsFP_DIV refers to x87 FP, and SIMD FP divide and square root operationsMMX_ALU refers to SIMD integer arithmetic and logic operationsMMX_SHFT handles Shift, Rotate, Shuffle, Pack and Unpack operationsMMX_MISC handles SIMD reciprocal and some integer operationsOM15151Figure 2-5. Execution Units and Ports in Out-Of-Order Core2-27