Intel® 64 and IA-32 Architectures Optimization Reference Manual

INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES“add” operation and load from logical processor 1 can be executed simultaneously bythe execution engine.In the first implementation of HT Technology, the physical execution resources areshared and the architecture state is duplicated for each logical processor. This minimizesthe die area cost of implementing HT Technology while still achieving performancegains for multithreaded applications or multitasking workloads.ArchitecturalStateArchitecturalStateArchitecturalStateArchitecturalStateExecution EngineExecution EngineLocal APICLocal APICLocal APICLocal APICBus InterfaceBus InterfaceSystem BusOM15152Figure 2-7. Hyper-Threading Technology on an SMPThe performance potential due to HT Technology is due to:• The fact that operating systems and user programs can schedule processes orthreads to execute simultaneously on the logical processors in each physicalprocessor• The ability to use on-chip execution resources at a higher level than when only asingle thread is consuming the execution resources; higher level of resourceutilization can lead to higher system throughput2.5.1 Processor Resources and HT TechnologyThe majority of microarchitecture resources in a physical processor are sharedbetween the logical processors. Only a few small data structures were replicated foreach logical processor. This section describes how resources are shared, partitionedor replicated.2-38