Intel® 64 and IA-32 Architectures Optimization Reference Manual

USING PERFORMANCE MONITORING EVENTS2nd-Level Cache Reads Hit Shared2nd-Level Cache Reads Hit Modified2nd-Level Cache Reads Hit Exclusive3rd-Level Cache Reads Hit Shared3rd-Level Cache Reads Hit Modified3rd-Level Cache Reads Hit ExclusiveBus Metrics Bus Accesses from the Processor 1Non-prefetch Bus Accesses from the Processor 1Reads from the Processor 1Writes from the Processor 1Reads Non-prefetch from the Processor 1Characterization MetricsTable B-12. Metrics Supporting Qualification byLogical Processor and Parallel CountingAll WC from the Processor 1All UC from the Processor 1Bus Accesses from All Agents 1Bus Accesses Underway from the processor 1Bus Reads Underway from the processor 1Non-prefetch Reads Underway from the processor 1All UC Underway from the processor 1All WC Underway from the processor 1Bus Writes Underway from the processor 1Bus Accesses Underway from All Agents 1Write WC Full (BSQ) 1Write WC Partial (BSQ) 1Writes WB Full (BSQ) 1Reads Non-prefetch Full (BSQ) 1Reads Invalidate Full- RFO (BSQ) 1UC Reads Chunk (BSQ) 1UC Reads Chunk Split (BSQ) 1UC Write Partial (BSQ) 1IO Reads Chunk (BSQ) 1IO Writes Chunk (BSQ) 1WB Writes Full Underway (BSQ) 1UC Reads Chunk Underway (BSQ) 1Write WC Partial Underway(BSQ) 1x87 Input Assistsx87 Output AssistsMachine Clear CountMemory Order Machine ClearSelf-Modifying Code ClearScalar DP RetiredScalar SP RetiredB-41