Intel® 64 and IA-32 Architectures Optimization Reference Manual

INSTRUCTION LATENCY AND THROUGHPUTWhile several items on the above list involve selecting the right instruction, thisappendix focuses on the following issues. These are listed in priority order, thoughwhich item contributes most to performance varies by application:• Maximize the flow of μops into the execution core. Instructions which consist ofmore than four μops require additional steps from microcode ROM. Instructionswith longer μop flows incur a delay in the front end and reduce the supply of μopsto the execution core.In Pentium 4 and Intel Xeon processors, transfers to microcode ROM oftenreduce how efficiently μops can be packed into the trace cache. Where possible,it is advisable to select instructions with four or fewer μops. For example, a32-bit integer multiply with a memory operand fits in the trace cache withoutgoing to microcode, while a 16-bit integer multiply to memory does not.• Avoid resource conflicts. Interleaving instructions so that they don’t compete forthe same port or execution unit can increase throughput. For example, alternatePADDQ and PMULUDQ (each has a throughput of one issue per two clock cycles).When interleaved, they can achieve an effective throughput of one instructionper cycle because they use the same port but different execution units. Selectinginstructions with fast throughput also helps to preserve issue port bandwidth,hide latency and allows for higher software performance.• Minimize the latency of dependency chains that are on the critical path. Forexample, an operation to shift left by two bits executes faster when encoded astwo adds than when it is encoded as a shift. If latency is not an issue, the shiftresults in a denser byte encoding.In addition to the general and specific rules, coding guidelines and the instructiondata provided in this manual, you can take advantage of the software performanceanalysis and tuning toolset available at http://developer.intel.com/software/products/index.htm.The tools include the Intel VTune Performance Analyzer, with itsperformance-monitoring capabilities.C.2 DEFINITIONSThe data is listed in several tables. The tables contain the following:• Instruction Name — The assembly mnemonic of each instruction.• Latency — The number of clock cycles that are required for the execution core tocomplete the execution of all of the μops that form an instruction.• Throughput — The number of clock cycles required to wait before the issueports are free to accept the same instruction again. For many instructions, thethroughput of an instruction can be significantly less than its latency.C-2