Intel® 64 and IA-32 Architectures Optimization Reference Manual

INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURES2.1.2 Front EndThe front ends needs to supply decoded instructions (μops) and sustain the streamto a six-issue wide out-of-order engine. The components of the front end, their functions,and the performance challenges to microarchitectural design are described inTable 2-1.Table 2-1. Components of the Front EndComponent Functions Performance ChallengesBranch PredictionUnit (BPU)• Helps the instruction fetch unitfetch the most likely instructionto be executed by predictingthe various branch types:conditional, indirect, direct, call,and return. Uses dedicatedhardware for each type.Instruction FetchUnitInstruction Queueand Decode Unit• Prefetches instructions that arelikely to be executed• Caches frequently-usedinstructions• Predecodes and buffersinstructions, maintaining aconstant bandwidth despiteirregularities in the instructionstream• Decodes up to four instructions,or up to five with macro-fusion• Stack pointer tracker algorithmfor efficient procedure entryand exit• Implements the Macro-Fusionfeature, providing higherperformance and efficiency• The Instruction Queue is alsoused as a loop cache, enablingsome loops to be executed withboth higher bandwidth andlower power• Enables speculativeexecution.• Improves speculativeexecution efficiency byreducing the amount ofcode in the “non-architectedpath” 1 to be fetched intothe pipeline.• Variable length instructionformat causes unevenness(bubbles) in decodebandwidth.• Taken branches andmisaligned targets causesdisruptions in the overallbandwidth delivered by thefetch unit.• Varying amounts of workper instruction requiresexpansion into variablenumbers of μops.• Prefix adds a dimension ofdecoding complexity.• Length Changing Prefix(LCP) can cause front endbubbles.NOTES:1. Code paths that the processor thought it should execute but then found out it should go inanother path and therefore reverted from its initial intention.2-5