Intel® 64 and IA-32 Architectures Optimization Reference Manual

OPTIMIZING CACHE USAGEmatic hardware prefetcher begins at half the trigger threshold distance and reachesmaximum benefit when the cache-miss stride is 64 bytes.Upperbound of Pointer-Chasing Latency Reduction120%100%Effective Latency Reduction80%60%40%20%Fam .15; M odel 3, 4Fam .15; M odel 0,1,2Fam. 6; Model 13Fam. 6; Model 14Fam. 15; Model 60%648096112128144160176192208224240Stride (Bytes)Figure 9-1. Effective Latency Reduction as a Function of Access Stride9.6.4 Example of Latency Hiding with S/W Prefetch InstructionAchieving the highest level of memory optimization using PREFETCH instructionsrequires an understanding of the architecture of a given machine. This section translatesthe key architectural implications into several simple guidelines for programmersto use.Figure 9-2 and Figure 9-3 show two scenarios of a simplified 3D geometry pipeline asan example. A 3D-geometry pipeline typically fetches one vertex record at a timeand then performs transformation and lighting functions on it. Both figures show twoseparate pipelines, an execution pipeline, and a memory pipeline (front-side bus).Since the Pentium 4 processor (similar to the Pentium II and Pentium III processors)completely decouples the functionality of execution and memory access, the twopipelines can function concurrently. Figure 9-2 shows “bubbles” in both the executionand memory pipelines. When loads are issued for accessing vertex data, the executionunits sit idle and wait until data is returned. On the other hand, the memory bussits idle while the execution units are processing vertices. This scenario severelydecreases the advantage of having a decoupled architecture.9-15