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Intel® 64 and IA-32 Architectures Optimization Reference Manual

Intel® 64 and IA-32 Architectures Optimization Reference Manual

Intel® 64 and IA-32 Architectures Optimization Reference Manual

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USING PERFORMANCE MONITORING EVENTSMetricStalls of Store BufferResources (nonst<strong>and</strong>ard3 )Table B-6. Performance Metrics - Characterization (Contd.)DescriptionNumber of allocationstalls due to lack ofstore buffersEvent Name or MetricExpressionResource_stallEvent Mask ValueRequiredSBFULL(Also set the followingCCCR bits: Compare=1;Edge=1;Threshold=0)NOTES:1. Most MMX technology instructions, Streaming SIMD Extensions <strong>and</strong> Streaming SIMD Extensions 2decode into a single mop. There are some instructions that decode into several mops; in these limitedcases, the metrics count the number of mops that are actually tagged.2. Most commonly used x87 instructions (e.g., fmul, fadd, fdiv, fsqrt, fstp, etc.) decode into a singlemop.However, transcendental <strong>and</strong> some x87 instructions decode into several mops; in these limitedcases, the metrics will count the number of mops that are actually tagged.3. This metric may not be supported in all models of the Pentium 4 processor family.Table B-7. Performance Metrics - Machine ClearMetric Description Event Name or MetricExpressionMachine Clear Count Number of cycles that Machine_clearentire pipeline of themachine is cleared forall causesMemory OrderMachine ClearSelf-modifying CodeClearNumber of timesentire pipeline of themachine is cleared dueto memory-orderingissuesNumber of timesentire pipeline of themachine is cleared dueto self-modifying codeissuesMachine_clearMachine_clearEvent Mask ValueRequiredCLEAR(Also set the followingCCCR bits: Compare=1;Edge=1; Threshold=0)MOCLEARSMCCLEARB-29

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