IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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INSTRUCTION LATENCY AND THROUGHPUTTable C-5. Streaming SIMD Extension Single-precisionFloating-point Instructions (Contd.)Instruction Latency 1 Throughput Execution Unit 2DisplayFamily_DisplayModel 0F_03H 0F_02H 0F_03H 0F_02H 0F_02HCOMISS xmm, xmm 7 6 2 2 FP_ADD,FP_MISCCVTPI2PS xmm, mm 12 11 2 4 MMX_ALU,FP_ADD,MMX_SHFTCVTPS2PI mm, xmm 8 7 2 2 FP_ADD,MMX_ALUCVTSI2SS 3 xmm, r32 12 11 2 2 FP_ADD,MMX_SHFT, MMX_MISCCVTSS2SI r32, xmm 9 8 2 2 FP_ADD,FP_MISCCVTTPS2PI mm, xmm 8 7 2 2 FP_ADD,MMX_ALUCVTTSS2SI r32, xmm 9 8 2 2 FP_ADD,FP_MISCDIVPS xmm, xmm 40 39 17 39 FP_DIVDIVSS xmm, xmm 32 23 17 23 FP_DIVMAXPS xmm, xmm 5 4 2 2 FP_ADDMAXSS xmm, xmm 5 4 2 2 FP_ADDMINPS xmm, xmm 5 4 2 2 FP_ADDMINSS xmm, xmm 5 4 2 2 FP_ADDMOVAPS xmm, xmm 6 6 1 1 FP_MOVEMOVHLPS 3 xmm, xmm 6 6 2 2 MMX_SHFTMOVLHPS 3 xmm, xmm 4 4 2 2 MMX_SHFTMOVMSKPS r32, xmm 6 6 2 2 FP_MISCMOVSS xmm, xmm 4 4 2 2 MMX_SHFTMOVUPS xmm, xmm 6 6 1 1 FP_MOVEMULPS xmm, xmm 7 6 2 2 FP_MULMULSS xmm, xmm 7 6 2 2 FP_MULORPS 3 xmm, xmm 4 4 2 2 MMX_ALURCPPS 3 xmm, xmm 6 6 4 4 MMX_MISCRCPSS 3 xmm, xmm 6 6 2 2 MMX_MISC,MMX_SHFTC-14
INSTRUCTION LATENCY AND THROUGHPUTTable C-5. Streaming SIMD Extension Single-precisionFloating-point Instructions (Contd.)Instruction Latency 1 Throughput Execution Unit 2DisplayFamily_DisplayModel 0F_03H 0F_02H 0F_03H 0F_02H 0F_02HRSQRTPS 3 xmm, xmm 6 6 4 4 MMX_MISCRSQRTSS 3 xmm, xmm 6 6 4 4 MMX_MISC,MMX_SHFTSHUFPS 3 xmm, xmm, imm8 6 6 2 2 MMX_SHFTSQRTPS xmm, xmm 40 39 40 39 FP_DIVSQRTSS xmm, xmm 32 23 32 23 FP_DIVSUBPS xmm, xmm 5 4 2 2 FP_ADDSUBSS xmm, xmm 5 4 2 2 FP_ADDUCOMISS xmm, xmm 7 6 2 2 FP_ADD, FP_MISCUNPCKHPS 3 xmm, xmm 6 6 2 2 MMX_SHFTUNPCKLPS 3 xmm, xmm 4 4 2 2 MMX_SHFTXORPS 3 xmm, xmm 4 4 2 2 MMX_ALUFXRSTOR 150FXSAVE 100See Appendix C.3.2Table C-5a. Streaming SIMD Extension Single-precisionFloating-point InstructionsInstruction Latency 1 ThroughputDisplayFamily_DisplayModel06_0FH06_0EH06_0DH06_09H 06_0FH06_0EH06_0DH06_09HADDPS xmm, xmm 3 4 4 4 1 2 2 2ADDSS xmm, xmm 3 3 3 3 1 1 1 1ANDNPS xmm, xmm 1 2 1 2ANDPS xmm, xmm 1 2 1 2CMPPS xmm, xmm 3 4 4 4 1 2 2 2CMPSS xmm, xmm 3 3 3 3 1 1 1 1COMISS xmm, xmm 1 1 1 1 1 1 1 1CVTPI2PS xmm, mm 3 3 3 3 1 1 1 1CVTPS2PI mm, xmm 3 3 1 1CVTSI2SS xmm, r32 4 4 1 2C-15
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESIn t
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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Page 394 and 395: USING PERFORMANCE MONITORING EVENTS
Page 432 and 433: INSTRUCTION LATENCY AND THROUGHPUTW
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Page 460 and 461: STACK ALIGNMENTThe solution to this
Page 462 and 463: STACK ALIGNMENTExample D-1. Aligned
Page 464 and 465: STACK ALIGNMENTExample D-2. Aligned
Page 466 and 467: STACK ALIGNMENTD-8
Page 468 and 469: SUMMARY OF RULES AND SUGGESTIONSret
Page 470 and 471: SUMMARY OF RULES AND SUGGESTIONSfou
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Page 476 and 477: SUMMARY OF RULES AND SUGGESTIONSCor
Page 478 and 479: SUMMARY OF RULES AND SUGGESTIONSE-1
Page 480 and 481: INDEXsummary of rules, E-1tuning hi
Page 482 and 483: INDEXevent ratios, B-50execution co
Page 484 and 485: INDEXprefetching, 8-5SFENCE instruc
Page 486 and 487: INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
Page 488 and 489: INDEXIndex-10
Page 490: Intel Corp.999 CANADA PLACE,Suite 4
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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