Intel® 64 and IA-32 Architectures Optimization Reference Manual

USING PERFORMANCE MONITORING EVENTSB.7.10Memory Sub-system - Bus CharacterizationB.7.10.1Bus Utilization54. Bus Utilization: BUS_TRANS_ANY.ALL_AGENTS * 2 / CPU_CLK_UNHALTED.BUS *100Bus Utilization is the percentage of bus cycles used for transferring bus transactionsof any type. In single processor systems most of the bus transactions carry data. Inmultiprocessor systems some of the bus transactions are used to coordinate cachestates to keep data coherency.55. Data Bus Utilization: BUS_DRDY_CLOCKS.ALL_AGENTS /CPU_CLK_UNHALTED.BUS * 100Data Bus Utilization is the percentage of bus cycles used for transferring data amongall bus agents in the system, including processors and memory. High bus utilizationindicates heavy traffic between the processor(s) and memory. Memory sub-systemlatency can impact the performance of the program. For compute-intensive applicationswith high bus utilization, look for opportunities to improve data and codelocality. For other types of applications (for example, copying large amounts of datafrom one memory area to another), try to maximize bus utilization.56. Bus Not Ready Ratio: BUS_BNR_DRV.ALL_AGENTS * 2 /CPU_CLK_UNHALTED.BUS * 100Bus Not Ready Ratio estimates the percentage of bus cycles during which new bustransactions cannot start. A high value for Bus Not Ready Ratio indicates that the busis highly loaded. As a result of the Bus Not Ready (BNR) signal, new bus transactionsmight defer and their latency will have higher impact on program performance.57. Burst Read in Bus Utilization: BUS_TRANS_BRD.SELF * 2 /CPU_CLK_UNHALTED.BUS * 100A high value for Burst Read in Bus Utilization indicates that bus and memory latencyof burst read operations may impact the performance of the program.58. RFO in Bus Utilization: BUS_TRANS_RFO.SELF * 2 / CPU_CLK_UNHALTED.BUS *100A high value for RFO in Bus Utilization indicates that latency of Read For Ownership(RFO) transactions may impact the performance of the program. RFO transactionsmay have a higher impact on the program performance compared to other burst readoperations (for example, as a result of loads that missed the L2). See also Ratio 31.B.7.10.2Modified Cache Lines Eviction59. L2 Modified Lines Eviction Rate: L2_M_LINES_OUT.SELF.ANY /INST_RETIRED.ANYWhen a new cache line is brought from memory, an existing cache line, possiblymodified, is evicted from the L2 cache to make space for the new line. Frequent evic-B-61