Intel® 64 and IA-32 Architectures Optimization Reference Manual

INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURESthe line is in exclusive or modified state). Then the processor looks for the cache linein the cache and memory sub-systems. The look-ups for the locality of load or storeoperation are in the following order:1. DCU of the initiating core2. DCU of the other core and second-level cache3. System memoryThe cache line is taken from the DCU of the other core only if it is modified, ignoringthe cache line availability or state in the L2 cache. Table 2-9 lists the performancecharacteristics of generic load and store operations in an Intel Core Duo processor.Numeric values of Table 2-9 are in terms of processor core cycles.Table 2-9. Characteristics of Load and Store Operationsin Intel Core Duo ProcessorsLoadStoreData Locality Latency Throughput Latency ThroughputDCU 3 1 2 1DCU of the other core in“Modified” state14 + bustransaction14 + bustransaction14 + bustransaction2nd-level cache 14