IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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OPTIMIZING CACHE USAGE• If a processor does not support the deterministic cache parameters and does notprovide a legacy prefetch size descriptor, then 32-bytes is the default size for alllevels of the cache hierarchy.9-40
CHAPTER 964-BIT MODE CODING GUIDELINES9.1 INTRODUCTIONThis chapter describes coding guidelines for application software written to run in64-bit mode. Some coding recommendations applicable to 64-bit mode are coveredin Chapter 3. The guidelines in this chapter should be considered as an addendum tothe coding guidelines described in Chapter 3 through Chapter 8.Software that runs in either compatibility mode or legacy non-64-bit modes shouldfollow the guidelines described in Chapter 3 through Chapter 8.9.2 CODING RULES AFFECTING 64-BIT MODE9.2.1 Use Legacy 32-Bit Instructions When Data Size Is 32 Bits64-bit mode makes 16 general purpose 64-bit registers available to applications. Ifapplication data size is 32 bits, there is no need to use 64-bit registers or 64-bit arithmetic.The default operand size for most instructions is 32 bits. The behavior of thoseinstructions is to make the upper 32 bits all zeros. For example, when zeroing out aregister, the following two instruction streams do the same thing, but the 32-bitversion saves one instruction byte:32-bit version:xor eax, eax; Performs xor on lower 32bits and zeroes the upper 32 bits.64-bit version:xor rax, rax; Performs xor on all 64 bits.This optimization holds true for the lower 8 general purpose registers: EAX, ECX,EBX, EDX, ESP, EBP, ESI, EDI. To access the data in registers R9-R15, the REX prefixis required. Using the 32-bit form there does not reduce code size.9-1
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESIn t
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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Page 282 and 283: MULTICORE AND HYPER-THREADING TECHN
Page 294 and 295: OPTIMIZING CACHE USAGE• Take adva
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Page 304 and 305: OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
Page 306 and 307: OPTIMIZING CACHE USAGE• The hardw
Page 308 and 309: OPTIMIZING CACHE USAGETimeExecution
Page 310 and 311: OPTIMIZING CACHE USAGEschedule pref
Page 312 and 313: OPTIMIZING CACHE USAGEtime is large
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Page 324 and 325: OPTIMIZING CACHE USAGE9.7.2.3 Concl
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Page 328 and 329: OPTIMIZING CACHE USAGEExample 9-11.
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Page 338 and 339: 64-BIT MODE CODING GUIDELINES9-6
Page 340 and 341: POWER OPTIMIZATION FOR MOBILE USAGE
Page 354 and 355: APPLICATION PERFORMANCE TOOLSThe /f
Page 356 and 357: APPLICATION PERFORMANCE TOOLSTable
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Page 366 and 367: APPLICATION PERFORMANCE TOOLSThe Li
Page 368 and 369: APPLICATION PERFORMANCE TOOLSA.5 IN
Page 370 and 371: USING PERFORMANCE MONITORING EVENTS
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUTo
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INSTRUCTION LATENCY AND THROUGHPUTT
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSto
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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