Intel® 64 and IA-32 Architectures Optimization Reference Manual

CONTENTSTABLESPAGETable 2-1. Components of the Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5Table 2-2. Issue Ports of Intel Core Microarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11Table 2-3. Cache Parameters of Processors based on Intel Core Microarchitecture . . . . . . . . 2-18Table 2-4. Characteristics of Load and Store Operations in Intel Core Microarchitecture . . . 2-18Table 2-5. Pentium 4 and Intel Xeon Processor Cache Parameters . . . . . . . . . . . . . . . . . . . . . . . 2-28Table 2-7. Cache Parameters of Pentium M, Intel Core Solo,and Intel Core Duo Processors. 2-35Table 2-6. Trigger Threshold and CPUID Signatures for Processor Families . . . . . . . . . . . . . . . 2-35Table 2-8. Family And Model Designations of Microarchitectures. . . . . . . . . . . . . . . . . . . . . . . . . 2-43Table 2-9. Characteristics of Load and Store Operations in Intel Core Duo Processors . . . . . 2-44Table 3-1.Store Forwarding Restrictions of Processors Based on Intel CoreMicroarchitecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54Table 5-1. PAHUF Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-16Table 6-1. SoA Form of Representing Vertices Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-5Table 8-1. Properties of Synchronization Objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-15Table 9-1. Software Prefetching Considerations into Strip-mining Code . . . . . . . . . . . . . . . . . . 8-26Table 9-2. Relative Performance of Memory Copy Routines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-36Table 9-3. Deterministic Cache Parameters Leaf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-38Table A-1. Recommended IA-32 Processor Optimization Options . . . . . . . . . . . . . . . . . . . . . . . . . . A-2Table A-2. Recommended Processor Optimization Options for 64-bit Code . . . . . . . . . . . . . . . . A-3Table A-3. Vectorization Control Switch Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-4Table B-1. Performance Metrics - General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-6Table B-2. Performance Metrics - Branching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-8Table B-3. Performance Metrics - Trace Cache and Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-9Table B-4. Performance Metrics - Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-12Table B-5. Performance Metrics - Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-17Table B-6. Performance Metrics - Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-27Table B-7. Performance Metrics - Machine Clear. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-29Table B-8. Metrics That Utilize Replay Tagging Mechanism. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-36Table B-9. Metrics That Utilize the Front-end Tagging Mechanism. . . . . . . . . . . . . . . . . . . . . . . . B-37Table B-10. Metrics That Utilize the Execution Tagging Mechanism. . . . . . . . . . . . . . . . . . . . . . . . B-37Table B-11. New Metrics for Pentium 4 Processor (Family 15, Model 3). . . . . . . . . . . . . . . . . . . . B-38Table B-12. Metrics Supporting Qualification by Logical Processor and Parallel Counting . . . . B-40Table B-13. Metrics Independent of Logical Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-42Table C-1. Supplemental Streaming SIMD Extension 3 SIMD Instructions . . . . . . . . . . . . . . . . . . .C-4Table C-2. Streaming SIMD Extension 3 SIMD Floating-point Instructions . . . . . . . . . . . . . . . . . . .C-5Table C-3. Streaming SIMD Extension 2 128-bit Integer Instructions . . . . . . . . . . . . . . . . . . . . . . .C-5Table C-4. Streaming SIMD Extension 2 Double-precision Floating-point Instructions . . . . . . C-10Table C-5. Streaming SIMD Extension Single-precision Floating-point Instructions. . . . . . . . . C-13Table C-6. Streaming SIMD Extension 64-bit Integer Instructions . . . . . . . . . . . . . . . . . . . . . . . . C-17Table C-7. MMX Technology 64-bit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-18Table C-8. MMX Technology 64-bit Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-19Table C-9. x87 Floating-point Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-21Table C-10. General Purpose Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-23xx