Intel® 64 and IA-32 Architectures Optimization Reference Manual

GENERAL OPTIMIZATION GUIDELINESproceed with fixed latencies. General guidelines to make use of the available parallelismare:• Follow the rules (see Section 3.4) to maximize useful decode bandwidth and frontend throughput. These rules include favouring single μop instructions and takingadvantage of micro-fusion, Stack pointer tracker and macro-fusion.• Maximize rename bandwidth. Guidelines are discussed in this section and includeproperly dealing with partial registers, ROB read ports and instructions whichcauses side-effects on flags.• Scheduling recommendations on sequences of instructions so that multipledependency chains are alive in the reservation station (RS) simultaneously, thusensuring that your code utilizes maximum parallelism.• Avoid hazards, minimize delays that may occur in the execution core, allowingthe dispatched μops to make progress and be ready for retirement quickly.3.5.1 Instruction SelectionSome execution units are not pipelined, this means that μops cannot be dispatchedin consecutive cycles and the throughput is less than one per cycle.It is generally a good starting point to select instructions by considering the numberof μops associated with each instruction, favoring in the order of: single-μop instructions,simple instruction with less then 4 μops, and last instruction requiring microsequencerROM (μops which are executed out of the microsequencer involve extraoverhead).Assembly/Compiler Coding Rule 28. (M impact, H generality) Favor singlemicro-operationinstructions. Also favor instruction with shorter latencies.A compiler may be already doing a good job on instruction selection. If so, user interventionusually is not necessary.Assembly/Compiler Coding Rule 29. (M impact, L generality) Avoid prefixes,especially multiple non-0F-prefixed opcodes.Assembly/Compiler Coding Rule 30. (M impact, L generality) Do not usemany segment registers.On the Pentium M processor, there is only one level of renaming of segment registers.Assembly/Compiler Coding Rule 31. (ML impact, M generality) Avoid usingcomplex instructions (for example, enter, leave, or loop) that have more than fourµops and require multiple cycles to decode. Use sequences of simple instructionsinstead.Complex instructions may save architectural registers, but incur a penalty of 4 µops toset up parameters for the microsequencer ROM in Intel NetBurst microarchitecture.Theoretically, arranging instructions sequence to match the 4-1-1-1 template appliesto processors based on Intel Core microarchitecture. However, with macro-fusionand micro-fusion capabilities in the front end, attempts to schedule instructionsequences using the 4-1-1-1 template will likely provide diminishing returns.3-25