Intel® 64 and IA-32 Architectures Optimization Reference Manual

GENERAL OPTIMIZATION GUIDELINESextended double-precision computation. These characteristics affect computationsincluding floating-point divide and square root.Assembly/Compiler Coding Rule 61. (H impact, L generality) Minimize thenumber of changes to the precision mode.3.8.3.3 Improving Parallelism and the Use of FXCHThe x87 instruction set relies on the floating point stack for one of its operands. If thedependence graph is a tree, which means each intermediate result is used only onceand code is scheduled carefully, it is often possible to use only operands that are onthe top of the stack or in memory, and to avoid using operands that are buried underthe top of the stack. When operands need to be pulled from the middle of the stack,an FXCH instruction can be used to swap the operand on the top of the stack withanother entry in the stack.The FXCH instruction can also be used to enhance parallelism. Dependent chains canbe overlapped to expose more independent instructions to the hardware scheduler.An FXCH instruction may be required to effectively increase the register name spaceso that more operands can be simultaneously live.In processors based on Intel NetBurst microarchitecture, however, that FXCH inhibitsissue bandwidth in the trace cache. It does this not only because it consumes a slot,but also because of issue slot restrictions imposed on FXCH. If the application is notbound by issue or retirement bandwidth, FXCH will have no impact.The effective instruction window size in processors based on Intel NetBurst microarchitectureis large enough to permit instructions that are as far away as the next iterationto be overlapped. This often obviates the need to use FXCH to enhanceparallelism.The FXCH instruction should be used only when it’s needed to express an algorithmor to enhance parallelism. If the size of register name space is a problem, the use ofXMM registers is recommended.Assembly/Compiler Coding Rule 62. (M impact, M generality) Use FXCH onlywhere necessary to increase the effective name space.This in turn allows instructions to be reordered and made available for execution inparallel. Out-of-order execution precludes the need for using FXCH to move instructionsfor very short distances.3.8.4 x87 vs. Scalar SIMD Floating-point Trade-offsThere are a number of differences between x87 floating-point code and scalarfloating-point code (using SSE and SSE2). The following differences should drivedecisions about which registers and instructions to use:• When an input operand for a SIMD floating-point instruction contains values thatare less than the representable range of the data type, a denormal exceptionoccurs. This causes a significant performance penalty. An SIMD floating-point3-84