Intel® 64 and IA-32 Architectures Optimization Reference Manual

MULTICORE AND HYPER-THREADING TECHNOLOGYExample 8-12. Assembling a Look up Table to Manage Affinity Masksand Schedule Threads to Each Core First (Contd.)/ Assemble the sequence for first LP consecutively to different core.while (j < NumStartedLPs) {// Determine the first LP in each core.if( ! apic_conf [j ].smt) { // This is the first LP in a core// supporting HT.LuT[index++] = apic_conf[j].affinitymask;}j++;}/// Now the we have assigned each core to consecutive indices,// we can finish the table to use the rest of the// LPs in each core.nThreadsPerCore = MaxLPPerPackage()/MaxCoresPerPackage();for (i = 0 ; i < nThreadsPerCore; i ++) {for (j = 0 ; j < NumStartedLPs; j += nThreadsPerCore) {// Set the affinity binding for another logical// processor in each core.}}}if( apic_conf[ i+j ].SMT) {LuT[ index++] = apic_id[ i+j ].affinitymask;}Example 8-13. Discovering the Affinity Masks for Sibling Logical ProcessorsSharing the Same Cache// Logical processors sharing the same cache can be determined by bucketing// the logical processors with a mask, the width of the mask is determined// from the maximum number of logical processors sharing that cache level.// The algorithm below assumes that all processors have identical cache hierarchy// and initial APIC ID assignment across the modular// boundary of the logical processor sharing the target level cache must respect// bit-field boundary. This is a requirement similar to those applying to// core boundary and package boundary. The modular boundary of those// logical processors sharing the target level cache may coincide with core// boundary or above core boundary.8-38