IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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OPTIMIZING FOR SIMD INTEGER APPLICATIONS5.7.1.1 Supplemental Techniques for Avoiding Cache Line SplitsVideo processing applications sometimes cannot avoid loading data from memoryaddresses that are not aligned to 16-byte boundaries. An example of this situation iswhen each line in a video frame is averaged by shifting horizontally half a pixel.Example shows a common operation in video processing that loads data frommemory address not aligned to a 16-byte boundary. As video processing traverseseach line in the video frame, it experiences a cache line split for each 64 byte chunkloaded from memory.Example 5-35. An Example of Video Processing with Cache Line Splits// Average half-pels horizonally (on // the “x” axis),// from one reference frame only.nextLinesLoop:movdqu xmm0, XMMWORD PTR [edx] // may not be 16B alignedmovdqu xmm0, XMMWORD PTR [edx+1]movdqu xmm1, XMMWORD PTR [edx+eax]movdqu xmm1, XMMWORD PTR [edx+eax+1]pavgbxmm0, xmm1pavgbxmm2, xmm3movdqaXMMWORD PTR [ecx], xmm0movdqaXMMWORD PTR [ecx+eax], xmm2// (repeat ...)SSE3 provides an instruction LDDQU for loading from memory address that are not16-byte aligned. LDDQU is a special 128-bit unaligned load designed to avoid cacheline splits. If the address of the load is aligned on a 16-byte boundary, LDQQU loadsthe 16 bytes requested. If the address of the load is not aligned on a 16-byteboundary, LDDQU loads a 32-byte block starting at the 16-byte aligned addressimmediately below the address of the load request. It then provides the requested 16bytes. If the address is aligned on a 16-byte boundary, the effective number ofmemory requests is implementation dependent (one, or more).LDDQU is designed for programming usage of loading data from memory withoutstoring modified data back to the same address. Thus, the usage of LDDQU should berestricted to situations where no store-to-load forwarding is expected. For situationswhere store-to-load forwarding is expected, use regular store/load pairs (eitheraligned or unaligned based on the alignment of the data accessed).5-34
OPTIMIZING FOR SIMD INTEGER APPLICATIONSExample 5-36. Video Processing Using LDDQU to Avoid Cache Line Splits// Average half-pels horizontally (on // the “x” axis),// from one reference frame only.nextLinesLoop:lddqu xmm0, XMMWORD PTR [edx] // may not be 16B alignedlddqu xmm0, XMMWORD PTR [edx+1]lddqu xmm1, XMMWORD PTR [edx+eax]lddqu xmm1, XMMWORD PTR [edx+eax+1]pavgbxmm0, xmm1pavgbxmm2, xmm3movdqaXMMWORD PTR [ecx], xmm0 //results stored elsewheremovdqaXMMWORD PTR [ecx+eax], xmm2// (repeat ...)5.7.2 Increasing Bandwidth of Memory Fills and Video FillsIt is beneficial to understand how memory is accessed and filled. A memory-tomemoryfill (for example a memory-to-video fill) is defined as a 64-byte (cache line)load from memory which is immediately stored back to memory (such as a videoframe buffer).The following are guidelines for obtaining higher bandwidth and shorter latencies forsequential memory fills (video fills). These recommendations are relevant for all Intelarchitecture processors with MMX technology and refer to cases in which the loadsand stores do not hit in the first- or second-level cache.5.7.2.1 Increasing Memory Bandwidth Using the MOVDQ InstructionLoading any size data operand will cause an entire cache line to be loaded into thecache hierarchy. Thus, any size load looks more or less the same from a memorybandwidth perspective. However, using many smaller loads consumes more microarchitecturalresources than fewer larger stores. Consuming too many resources cancause the processor to stall and reduce the bandwidth that the processor can requestof the memory subsystem.Using MOVDQ to store the data back to UC memory (or WC memory in some cases)instead of using 32-bit stores (for example, MOVD) will reduce by three-quarters thenumber of stores per memory fill cycle. As a result, using the MOVDQ in memory fillcycles can achieve significantly higher effective bandwidth than using MOVD.5-35
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURES4.3.1
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CODING FOR SIMD ARCHITECTURESExampl
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUT
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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