Intel® 64 and IA-32 Architectures Optimization Reference Manual

GENERAL OPTIMIZATION GUIDELINESThe instruction MOV DX, 01234h is subject to LCP stalls in processors based on IntelCore microarchitecture, and in Intel Core Duo and Intel Core Solo processors.Instructions that contain imm16 as part of their fixed encoding but do not require LCPto change the immediate size are not subject to LCP stalls. The REX prefix (4xh) in64-bit mode can change the size of two classes of instruction, but does not cause anLCP penalty.If the LCP stall happens in a tight loop, it can cause significant performance degradation.When decoding is not a bottleneck, as in floating-point heavy code, isolated LCPstalls usually do not cause performance degradation.Assembly/Compiler Coding Rule 21. (MH impact, MH generality) Favorgenerating code using imm8 or imm32 values instead of imm16 values.If imm16 is needed, load equivalent imm32 into a register and use the word value inthe register instead.Double LCP StallsInstructions that are subject to LCP stalls and cross a 16-byte fetch line boundary cancause the LCP stall to trigger twice. The following alignment situations can cause LCPstalls to trigger twice:• An instruction is encoded with a MODR/M and SIB byte, and the fetch lineboundary crossing is between the MODR/M and the SIB bytes.• An instruction starts at offset 13 of a fetch line references a memory locationusing register and immediate byte offset addressing mode.The first stall is for the 1st fetch line, and the 2nd stall is for the 2nd fetch line. Adouble LCP stall causes a decode penalty of 11 cycles.The following examples cause LCP stall once, regardless of their fetch-line location ofthe first byte of the instruction:ADD DX, 01234HADD word ptr [EDX], 01234HADD word ptr 012345678H[EDX], 01234HADD word ptr [012345678H], 01234HThe following instructions cause a double LCP stall when starting at offset 13 of afetch line:ADD word ptr [EDX+ESI], 01234HADD word ptr 012H[EDX], 01234HADD word ptr 012345678H[EDX+ESI], 01234HTo avoid double LCP stalls, do not use instructions subject to LCP stalls that use SIBbyte encoding or addressing mode with byte displacement.False LCP StallsFalse LCP stalls have the same characteristics as LCP stalls, but occur on instructionsthat do not have any imm16 value.3-22