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Intel® 64 and IA-32 Architectures Optimization Reference Manual

Intel® 64 and IA-32 Architectures Optimization Reference Manual

Intel® 64 and IA-32 Architectures Optimization Reference Manual

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OPTIMIZING FOR SIMD INTEGER APPLICATIONSExample 5-5. Signed Unpack Code (Contd.)movdqa xmm1, xmm0 ; copy sourcepunpcklwd xmm0, xmm0 ; unpack four low end words of the source; into the upper 16 bits of each doubleword; in the destinationpunpckhwd xmm1, xmm1 ; unpack 4 high-end words of the source; into the upper 16 bits of each doubleword; in the destinationpsrad xmm0, 16 ; sign-extend the 4 low-end words of the source; into four <strong>32</strong>-bit signed doublewordspsrad xmm1, 16 ; sign-extend the 4 high-end words of the; source into four <strong>32</strong>-bit signed doublewords5.4.3 Interleaved Pack with SaturationPack instructions pack two values into a destination register in a predeterminedorder. PACKSSDW saturates two signed doublewords from a source oper<strong>and</strong> <strong>and</strong> twosigned doublewords from a destination oper<strong>and</strong> into four signed words; <strong>and</strong> it packsthe four signed words into a destination register. See Figure 5-1.SSE2 extends PACKSSDW so that it saturates four signed doublewords from a sourceoper<strong>and</strong> <strong>and</strong> four signed doublewords from a destination oper<strong>and</strong> into eight signedwords; the eight signed words are packed into the destination.mm/m<strong>64</strong>mmD C B AD 1C 1B 1A 1mmOM15159Figure 5-1. PACKSSDW mm, mm/mm<strong>64</strong> InstructionFigure 5-2 illustrates where two pairs of values are interleaved in a destinationregister; Example 5-6 shows MMX code that accomplishes the operation.5-8

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