Intel® 64 and IA-32 Architectures Optimization Reference Manual

INSTRUCTION LATENCY AND THROUGHPUTTable C-9. x87 Floating-point Instructions (Contd.)Instruction Latency 1 Throughput Execution Unit 2DisplayFamily_DisplayModel0F_03H 0F_02H 0F_03H 0F_02H 0F_02HFINCSTP/FDECSTP 6 0See Appendix C.3.2, “Table Footnotes”Table C-9a. x87 Floating-point InstructionsInstruction Latency 1 ThroughputDisplayFamily_DisplayModel06_0FH06_0EH06_0DH06_09H06_0FH06_0EH06_0DH06_09HFABS 1 1 1 1 1 1 1 1FADD 3 3 3 3 1 1 1FSUB 3 3 3 3 1 1 1 1FMUL 5 5 5 5 2 2 2 2FCOM 1 1 1 1 1 1 1 1FCHSFDIV Single Precision 18 17FDIV Double Precision 32 31FDIV Extended Precision 38 37FSQRT Single Precision 29 28FSQRT Double Precision 58 58 58 58 58 58 58 58F2XM1 4 69 69 69 67 67 67FCOS 4 119 119 119 117 117 117FPATAN 4 147 147 147 147 147 147FPTAN 4 123 123 123 83 83 83FSIN 4 119 119 119 116 116 116FSINCOS 4 119 119 119 85 85 85FYL2X 4 96 96 96 92 92 92FYL2XP1 4 98 98 98 93 93 93FSCALE 4 17 17 17 15 15 15FRNDINT 4 21 21 21 20 20 20FXCH 5FLDZ 6 1 1 1 1 1 1 1 1FINCSTP/FDECSTP 6 1 1 1 1 1 1C-22