Intel® 64 and IA-32 Architectures Optimization Reference Manual

USING PERFORMANCE MONITORING EVENTSTable B-12. Metrics Supporting Qualification byLogical Processor and Parallel CountingPacked DP RetiredPacked SP Retired128-bit MMX Instructions Retired64-bit MMX Instructions Retiredx87 Instructions RetiredStalled Cycles of Store Buffer ResourcesStalls of Store Buffer ResourcesNOTES:1. Parallel counting is not supported due to ESCR restrictions.General MetricsTC and Front End MetricsMemory MetricsBus MetricsCharacterization MetricsTable B-13. Metrics Independent of Logical ProcessorsNon-Sleep Clock TicksPage Walk Miss ITLBPage Walk DTLB All MissesAll WCB EvictionsWCB Full EvictionsBus Data Ready from the ProcessorSSE Input AssistsB.5 USING PERFORMANCE EVENTS OF INTEL CORE SOLOAND INTEL CORE DUO PROCESSORSThere are performance events specific to the microarchitecture of Intel Core Solo andIntel Core Duo processors. See also: Appendix A of the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 3B).B.5.1Understanding the Results in a Performance CounterEach performance event detects a well-defined microarchitectural condition occurringin the core while the core is active. A core is active when:• It’s running code (excluding the halt instruction).• It’s being snooped by the other core or a logical processor on the platform. Thiscan also happen when the core is halted.Some microarchitectural conditions are applicable to a sub-system shared by morethan one core and some performance events provide an event mask (or unit mask)B-42