IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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MULTICORE AND HYPER-THREADING TECHNOLOGYExample 8-2. Basic Structure of Implementing Producer Consumer Threads (Contd.)}b) Basic structure of a consumer threadvoid consumer_thread(){ int mode2 = 0; // first iteration start with buffer 0, than alternateint iter_num = workamount - 1;while (iter_num--) {}WaitForSignal(&signal1);consume(buffs[mode2],count); // placeholder functionSignal(&end1,1);mode2 = 1 - mode2;}consume(buffs[mode2],count);It is possible to structure the producer-consumer model in an interlaced manner suchthat it can minimize bus traffic and be effective on multicore processors withoutshared second-level cache.In this interlaced variation of the producer-consumer model, each scheduling quantaof an application thread comprises of a producer task and a consumer task. Two identicalthreads are created to execute in parallel. During each scheduling quanta of athread, the producer task starts first and the consumer task follows after the completionof the producer task; both tasks work on the same buffer. As each taskcompletes, one thread signals to the other thread notifying its corresponding task touse its designated buffer. Thus, the producer and consumer tasks execute in parallelin two threads. As long as the data generated by the producer reside in either thefirst or second level cache of the same core, the consumer can access them withoutincurring bus traffic. The scheduling of the interlaced producer-consumer model isshown in Figure 8-4.Thread 0P(1)C(1)P(1)C(1)P(1)Thread 1P(2)C(2)P(2)C(2)Figure 8-4. Interlaced Variation of the Producer Consumer Model8-8
MULTICORE AND HYPER-THREADING TECHNOLOGYExample 8-3 shows the basic structure of a thread function that can be used in thisinterlaced producer-consumer model.Example 8-3. Thread Function for an Interlaced Producer Consumer Model// master thread starts first iteration, other thread must wait// one iterationvoid producer_consumer_thread(int master){int mode = 1 - master; // track which thread and its designated// buffer indexunsigned int iter_num = workamount >> 1;unsigned int i=0;iter_num += master & workamount & 1;if (master) // master thread starts the first iteration{produce(buffs[mode],count);Signal(sigp[1-mode1],1); // notify producer task in follower// thread that it can proceedconsume(buffs[mode],count);Signal(sigc[1-mode],1);i = 1;}for (; i < iter_num; i++){WaitForSignal(sigp[mode]);produce(buffs[mode],count); // notify the producer task in// other threadSignal(sigp[1-mode],1);}WaitForSignal(sigc[mode]);consume(buffs[mode],count);Signal(sigc[1-mode],1);}8-9
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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INSTRUCTION LATENCY AND THROUGHPUTW
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INSTRUCTION LATENCY AND THROUGHPUT
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INSTRUCTION LATENCY AND THROUGHPUTC
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STACK ALIGNMENTThe solution to this
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STACK ALIGNMENTExample D-1. Aligned
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STACK ALIGNMENTExample D-2. Aligned
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STACK ALIGNMENTD-8
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SUMMARY OF RULES AND SUGGESTIONSret
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SUMMARY OF RULES AND SUGGESTIONSfou
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SUMMARY OF RULES AND SUGGESTIONSvar
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SUMMARY OF RULES AND SUGGESTIONSCor
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SUMMARY OF RULES AND SUGGESTIONSE-1
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INDEXsummary of rules, E-1tuning hi
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INDEXevent ratios, B-50execution co
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INDEXprefetching, 8-5SFENCE instruc
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INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
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INDEXIndex-10
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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