IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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INSTRUCTION LATENCY AND THROUGHPUTTable C-5a. Streaming SIMD Extension Single-precisionFloating-point Instructions (Contd.)Instruction Latency 1 ThroughputDisplayFamily_DisplayModel06_0FH06_0EH06_0DH06_09H06_0FH06_0EH06_0DH06_09HCVTSS2SI r32, xmm 3 4 4 4 1 1 1 1CVT[T]SS2SI r64, 4 N/A N/A N/A 1 N/A N/A N/AxmmCVTTPS2PI mm, xmm 3 3 3 3 1 1 1 1CVTTSS2SI r32, xmm 3 4 4 4 1 1 1 1DIVPS xmm, xmm 18 35 35 35 17 34 34 34DIVSS xmm, xmm 18 18 18 18 17 17 17 17MAXPS xmm, xmm 3 4 4 4 1 2 2 2MAXSS xmm, xmm 3 3 3 3 1 1 1 1MINPS xmm, xmm 3 4 4 4 1 2 2 2MINSS xmm, xmm 3 3 3 3 1 1 1 1MOVAPS xmm, xmm 1 1 1 1 0.33 1 1 1MOVHLPS xmm, xmm 1 1 1 1 1 0.5 0.5 0.5MOVLHPS xmm, xmm 1 1 1 1 1 0.5 0.5 0.5MOVMSKPS r32, xmm 1 1 1 1 1 1 1 1MOVMSKPS r64, xmm 1 N/A N/A N/A 1 N/A N/A N/AMOVSS xmm, xmm 1 1 1 1 0.33 0.5 0.5 0.5MOVUPS xmm, xmm 1 1 1 1 0.5 1 1 1MULPS xmm, xmm 4 5 5 5 1 2 2 2MULSS xmm, xmm 4 4 4 4 1 1 1 1ORPS xmm, xmm 1 2 0.33 2RCPPS xmm, xmm 3 2 1 2RCPSS xmm, xmm 3 1 1 1RSQRTPS xmm, xmm 3 2 2 2RSQRTSS xmm, xmm 3 2 1SHUFPS xmm, xmm, 4 2 3 2imm8SQRTPS xmm, xmm 29 29+28 28 58SQRTSS xmm, xmm 29 30 28 29SUBPS xmm, xmm 3 4 1 2SUBSS xmm, xmm 3 3 1 1C-16
INSTRUCTION LATENCY AND THROUGHPUTTable C-5a. Streaming SIMD Extension Single-precisionFloating-point Instructions (Contd.)Instruction Latency 1 ThroughputDisplayFamily_DisplayModel06_0FH06_0EH06_0DH06_09H06_0FH06_0EH06_0DHUCOMISS xmm, xmm 1 1 1 1UNPCKHPS xmm, xmm 4 3 3 2UNPCKLPS xmm, xmm 4 3 3 2XORPS xmm, xmm 1 2 0.33 2FXRSTORFXSAVESee Appendix C.3.2, “Table Footnotes”06_09HTable C-6. Streaming SIMD Extension 64-bit Integer InstructionsInstruction Latency 1 Throughput Execution UnitCPUID 0F_03H 0F_02H 0F_03H 0F_02H 0F_02HPAVGB/PAVGW mm, mm 2 2 1 1 MMX_ALUPEXTRW r32, mm, imm8 7 7 2 2 MMX_SHFT,FP_MISCPINSRW mm, r32, imm8 4 4 1 1 MMX_SHFT,MMX_MISCPMAX mm, mm 2 2 1 1 MMX_ALUPMIN mm, mm 2 2 1 1 MMX_ALUPMOVMSKB 3 r32, mm 7 7 2 2 FP_MISCPMULHUW 3 mm, mm 9 8 1 1 FP_MULPSADBW mm, mm 4 4 1 1 MMX_ALUPSHUFW mm, mm, imm8 2 2 1 1 MMX_SHFTSee Appendix C.3.2, “Table Footnotes”C-17
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NIntel® 64 and IA-32 Architectures
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CONTENTS2.3.1 Front End. . . . . .
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CONTENTS3.7 PREFETCHING . . . . . .
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CONTENTS5.7.2.1 Increasing Memory B
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CONTENTS9.5.3 Streaming Store Instr
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CONTENTSB.7.4.3B.7.4.4B.7.4.5B.7.4.
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CONTENTSExample 4-1. Identification
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CONTENTSExample 9-8. Using HW Prefe
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CONTENTSFigure 9-7. Cache Blocking
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CHAPTER 1INTRODUCTIONThe Intel® 64
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INTRODUCTION• Chapter 10: Power O
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CHAPTER 2INTEL ® 64 AND IA-32 PROC
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INTEL® 64 AND IA-32 PROCESSOR ARCH
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CHAPTER 3GENERAL OPTIMIZATION GUIDE
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GENERAL OPTIMIZATION GUIDELINESThe
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GENERAL OPTIMIZATION GUIDELINEScomp
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GENERAL OPTIMIZATION GUIDELINES•
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GENERAL OPTIMIZATION GUIDELINESExam
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GENERAL OPTIMIZATION GUIDELINESthro
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GENERAL OPTIMIZATION GUIDELINESAsse
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GENERAL OPTIMIZATION GUIDELINESpred
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GENERAL OPTIMIZATION GUIDELINESIn t
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GENERAL OPTIMIZATION GUIDELINESBeca
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GENERAL OPTIMIZATION GUIDELINESInst
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GENERAL OPTIMIZATION GUIDELINESXOR
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GENERAL OPTIMIZATION GUIDELINESUse
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GENERAL OPTIMIZATION GUIDELINESMOVS
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GENERAL OPTIMIZATION GUIDELINESPack
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GENERAL OPTIMIZATION GUIDELINES3.5.
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GENERAL OPTIMIZATION GUIDELINESFor
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GENERAL OPTIMIZATION GUIDELINESAs a
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESmore
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GENERAL OPTIMIZATION GUIDELINESrequ
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GENERAL OPTIMIZATION GUIDELINESmiss
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINESpref
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GENERAL OPTIMIZATION GUIDELINES—
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GENERAL OPTIMIZATION GUIDELINESTher
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GENERAL OPTIMIZATION GUIDELINESstat
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GENERAL OPTIMIZATION GUIDELINESexte
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GENERAL OPTIMIZATION GUIDELINESFor
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CODING FOR SIMD ARCHITECTURES4.1.1
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CODING FOR SIMD ARCHITECTURESSoftwa
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CODING FOR SIMD ARCHITECTURESTo use
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURESmance
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CODING FOR SIMD ARCHITECTURESpurpos
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CODING FOR SIMD ARCHITECTURESIf the
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CODING FOR SIMD ARCHITECTURESExampl
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CODING FOR SIMD ARCHITECTURES• Us
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CODING FOR SIMD ARCHITECTURESpatter
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CODING FOR SIMD ARCHITECTURESmoves
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CODING FOR SIMD ARCHITECTURES4-28
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OPTIMIZING FOR SIMD INTEGER APPLICA
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OPTIMIZING FOR SIMD FLOATING-POINT
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MULTICORE AND HYPER-THREADING TECHN
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OPTIMIZING CACHE USAGE• Take adva
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OPTIMIZING CACHE USAGEHardware pref
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OPTIMIZING CACHE USAGEThe non-tempo
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OPTIMIZING CACHE USAGE9.5.1.3 Memor
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OPTIMIZING CACHE USAGENOTEFailure t
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OPTIMIZING CACHE USAGE9.5.5 CLFLUSH
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OPTIMIZING CACHE USAGE• The hardw
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OPTIMIZING CACHE USAGETimeExecution
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OPTIMIZING CACHE USAGEschedule pref
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OPTIMIZING CACHE USAGEtime is large
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OPTIMIZING CACHE USAGEresource stal
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OPTIMIZING CACHE USAGEPrefetchntaDa
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OPTIMIZING CACHE USAGEExample 9-7.
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OPTIMIZING CACHE USAGEA characteris
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OPTIMIZING CACHE USAGE9.7 MEMORY OP
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OPTIMIZING CACHE USAGE9.7.2.3 Concl
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OPTIMIZING CACHE USAGEis not reside
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OPTIMIZING CACHE USAGEExample 9-11.
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OPTIMIZING CACHE USAGETable 9-3. De
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OPTIMIZING CACHE USAGE• If a proc
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64-BIT MODE CODING GUIDELINESAssemb
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64-BIT MODE CODING GUIDELINESinstru
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64-BIT MODE CODING GUIDELINES9-6
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POWER OPTIMIZATION FOR MOBILE USAGE
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APPLICATION PERFORMANCE TOOLSThe /f
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APPLICATION PERFORMANCE TOOLSTable
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APPLICATION PERFORMANCE TOOLSA.1.6.
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSExampl
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APPLICATION PERFORMANCE TOOLSprogra
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APPLICATION PERFORMANCE TOOLSThe Li
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APPLICATION PERFORMANCE TOOLSA.5 IN
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USING PERFORMANCE MONITORING EVENTS
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Page 396 and 397: USING PERFORMANCE MONITORING EVENTS
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Page 460 and 461: STACK ALIGNMENTThe solution to this
Page 462 and 463: STACK ALIGNMENTExample D-1. Aligned
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Page 468 and 469: SUMMARY OF RULES AND SUGGESTIONSret
Page 470 and 471: SUMMARY OF RULES AND SUGGESTIONSfou
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Page 476 and 477: SUMMARY OF RULES AND SUGGESTIONSCor
Page 478 and 479: SUMMARY OF RULES AND SUGGESTIONSE-1
Page 480 and 481: INDEXsummary of rules, E-1tuning hi
Page 482 and 483: INDEXevent ratios, B-50execution co
Page 484 and 485: INDEXprefetching, 8-5SFENCE instruc
Page 486 and 487: INDEXPMAXSW, 5-28PMAXUB, 5-28PMINSW
Page 488 and 489: INDEXIndex-10
Page 490: Intel Corp.999 CANADA PLACE,Suite 4
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IntelÂ® 64 and IA-32 Architectures Optimization Reference Manual

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