Intel® 64 and IA-32 Architectures Optimization Reference Manual

CHAPTER 9OPTIMIZING CACHE USAGEOver the past decade, processor speed has increased. Memory access speed hasincreased at a slower pace. The resulting disparity has made it important to tuneapplications in one of two ways: either (a) a majority of data accesses are fulfilledfrom processor caches, or (b) effectively masking memory latency to utilize peakmemory bandwidth as much as possible.Hardware prefetching mechanisms are enhancements in microarchitecture to facilitatethe latter aspect, and will be most effective when combined with softwaretuning. The performance of most applications can be considerably improved if thedata required can be fetched from the processor caches or if memory traffic can takeadvantage of hardware prefetching effectively.Standard techniques to bring data into the processor before it is needed involve additionalprogramming which can be difficult to implement and may require specialsteps to prevent performance degradation. Streaming SIMD Extensions addressedthis issue by providing various prefetch instructions.Streaming SIMD Extensions introduced the various non-temporal store instructions.SSE2 extends this support to new data types and also introduce non-temporal storesupport for the 32-bit integer registers.This chapter focuses on:• Hardware Prefetch Mechanism, Software Prefetch and Cacheability Instructions— Discusses microarchitectural feature and instructions that allow you to affectdata caching in an application.• Memory Optimization Using Hardware Prefetching, Software Prefetch and CacheabilityInstructions — Discusses techniques for implementing memory optimizationsusing the above instructions.NOTEIn a number of cases presented, the prefetching and cache utilizationdescribed are specific to current implementations of Intel NetBurstmicroarchitecture but are largely applicable for the future processors.• Using deterministic cache parameters to manage cache hierarchy.9.1 GENERAL PREFETCH CODING GUIDELINESThe following guidelines will help you to reduce memory traffic and utilize peakmemory system bandwidth more effectively when large amounts of data movementmust originate from the memory system:9-1