Intel® 64 and IA-32 Architectures Optimization Reference Manual

INTEL® 64 AND IA-32 PROCESSOR ARCHITECTURESThe Stack Pointer Tracker moves all these implicit RSP updates to logic contained inthe decoders themselves. The feature provides the following benefits:• Improves decode bandwidth, as PUSH, POP and RET are single μop instructionsin Intel Core microarchitecture.• Conserves execution bandwidth as the RSP updates do not compete for executionresources.• Improves parallelism in the out of order execution engine as the implicit serialdependencies between μops are removed.• Improves power efficiency as the RSP updates are carried out on small, dedicatedhardware.2.1.2.6 Micro-fusionMicro-fusion fuses multiple μops from the same instruction into a single complexμop. The complex μop is dispatched in the out-of-order execution core. Micro-fusionprovides the following performance advantages:• Improves instruction bandwidth delivered from decode to retirement.• Reduces power consumption as the complex μop represents more work in asmaller format (in terms of bit density), reducing overall “bit-toggling” in themachine for a given amount of work and virtually increasing the amount ofstorage in the out-of-order execution engine.Many instructions provide register flavors and memory flavors. The flavor involving amemory operand will decodes into a longer flow of μops than the register version.Micro-fusion enables software to use memory to register operations to express theactual program behavior without worrying about a loss of decode bandwidth.2.1.3 Execution CoreThe execution core of the Intel Core microarchitecture is superscalar and can processinstructions out of order. When a dependency chain causes the machine to wait for aresource (such as a second-level data cache line), the execution core executes otherinstructions. This increases the overall rate of instructions executed per cycle (IPC).The execution core contains the following three major components:• Renamer — Moves μops from the front end to the execution core. Architecturalregisters are renamed to a larger set of microarchitectural registers. Renamingeliminates false dependencies known as read-after-read and write-after-readhazards.• Reorder buffer (ROB) — Holds μops in various stages of completion, bufferscompleted μops, updates the architectural state in order, and manages orderingof exceptions. The ROB has 96 entries to handle instructions in flight.2-9