Intel® 64 and IA-32 Architectures Optimization Reference Manual

USING PERFORMANCE MONITORING EVENTStions of modified lines from the L2 cache increase the latency of the L2 cache missesand consume bus bandwidth.60. Explicit WB in Bus Utilization: BUS_TRANS_WB.SELF * 2 /CPU_CLK_UNHALTED.BUS*100Explicit Write-back in Bus Utilization considers modified cache line evictions not onlyfrom the L2 cache but also from the L1 data cache. It represents the percentage ofbus cycles used for explicit write-backs from the processor to memory.B-62